# US 2014/0197464 A1 · Cmos image sensor and method of manufacturing the same

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- Number: US 2014/0197464 A1
- Document ID: US20140197464A1
- Status: Published application
- Kind: A1
- Application number: 14/158,121
- Filed: 2014-01-17
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hisanori IHARA
- Web page: https://patentgrep.com/patent/US20140197464A1

## CPC

- H10F 39/80373: {characterised by the gate of the transistor}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/8033: {Photosensitive area}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A CMOS image sensor has a photodiode including first and second impurity layers sequentially formed on a substrate, an isolation layer on the second impurity layer, and a transfer gate structure through the second impurity layer. The transfer gate structure contacts a top surface of the first impurity layer and a portion of the second impurity layer and includes a bottom surface having a step shape.

## Claims

### Claim 1

A CMOS image sensor, comprising:
a photodiode including a first impurity layer and a second impurity layer sequentially formed on a substrate;
an isolation layer on the second impurity layer; and
a transfer gate structure through the second impurity layer, the transfer gate structure contacting a top surface of the first impurity layer and a portion of the second impurity layer, the transfer gate structure including a bottom surface having a step shape.

### Claim 2 (depends on 1)

The CMOS image sensor as claimed in claim 1, wherein the transfer gate structure includes a gate electrode and a gate dielectric layer beneath the gate electrode.

### Claim 3 (depends on 2)

The CMOS image sensor as claimed in claim 2, wherein the gate electrode includes a lower portion, a central portion, and an upper portion thereof.

### Claim 4 (depends on 3)

The CMOS image sensor as claimed in claim 3, wherein:
the lower portion of the gate electrode contacts the top surface of the first impurity layer via the gate dielectric layer,
the central portion of the gate electrode contacts a portion of the second impurity layer via the gate dielectric layer, and
the upper portion of the gate electrode contacts a top surface of the second impurity layer and a top surface of the isolation layer via the gate dielectric layer.

### Claim 5 (depends on 3)

The CMOS image sensor as claimed in claim 3, wherein a portion of the lower portion of the gate electrode is not in an overlapping relationship with the upper portion of the gate electrode, when viewed from a top side.

### Claim 6 (depends on 3)

The CMOS image sensor as claimed in claim 3, wherein a portion of the central portion of the gate electrode is not in an overlapping relationship with the upper portion of the gate electrode, when viewed from a top side.

### Claim 7 (depends on 1)

The CMOS image sensor as claimed in claim 1, wherein the first impurity layer and the second impurity layer include different conductivity type impurities from each other.

### Claim 8

A method of manufacturing a CMOS image sensor, the method comprising:
sequentially forming a first impurity layer and second impurity layer on a substrate;
forming an isolation layer on the second impurity layer; and
forming a transfer gate structure through the second impurity layer, the transfer gate structure contacting a top surface of the first impurity layer and a portion of the second impurity layer, the transfer gate structure including a bottom surface having a step shape.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein forming the transfer gate structure includes forming a gate dielectric layer and a gate electrode sequentially stacked.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein forming the gate electrode includes forming a lower portion, a central portion, and an upper portion thereof.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein forming the gate dielectric layer and the gate electrode sequentially stacked includes:
removing a portion of the second impurity layer to expose the top surface of the first impurity layer;
forming the gate dielectric layer on the exposed top surface of the first impurity layer and on the second impurity layer; and
forming the gate electrode on the gate dielectric layer.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein the gate dielectric layer is further formed on the isolation layer.

### Claim 13 (depends on 8)

The method as claimed in claim 8, wherein the first impurity layer and the second impurity layer are formed to include different conductivity type impurities from each other, and form a photodiode.

### Claim 14

A CMOS image sensor, comprising:
a first impurity layer;
a second impurity layer on the first impurity layer, the first impurity layer and the second impurity layer forming a photodiode;
an isolation layer on the second impurity layer, portions of the second impurity layer and the isolation layer being absent above the first impurity layer such that a portion of the first impurity layer is exposed and such that the second impurity layer includes steps between the exposed first impurity layer and a top surface of the second impurity layer; and
a transfer gate structure extending through the second impurity layer, the transfer gate structure contacting the exposed top surface of the first impurity layer and the steps of the second impurity layer, the transfer gate structure including a bottom surface having a step shape complementary to the steps of the second impurity layer.

### Claim 15 (depends on 14)

The CMOS image sensor as claimed in claim 14, wherein the transfer gate structure includes a gate electrode and a gate dielectric layer beneath the gate electrode.

### Claim 16 (depends on 14)

The CMOS image sensor as claimed in claim 14, wherein:
a lower portion of the transfer gate structure contacts the top surface of the first impurity layer,
a central portion of the transfer gate structure contacts the steps of the second impurity layer, and
an upper portion of the transfer gate structure contacts a top surface of the second impurity layer and a top surface of the isolation layer.

### Claim 17 (depends on 16)

The CMOS image sensor as claimed in claim 16, wherein a portion of the upper portion of the transfer gate structure does not overlap part of the lower portion and central portion of the transfer gate structure, when viewed from a top side.

### Claim 18 (depends on 16)

The CMOS image sensor as claimed in claim 16, further comprising an insulation layer covering the transfer gate structure and exposed portions of the isolation layer.

### Claim 19 (depends on 14)

The CMOS image sensor as claimed in claim 14, wherein the first impurity layer and the second impurity layer include different conductivity type impurities from each other.