# US 2014/0197462 A1 · III-Nitride Transistor with High Resistivity Substrate

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- Number: US 2014/0197462 A1
- Document ID: US20140197462A1
- Status: Published application
- Kind: A1
- Application number: 14/188,316
- Filed: 2014-02-24
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: International Rectifier Corporation
- Applicants: International Rectifier Corporation
- Inventors: Michael A. Briere
- Web page: https://patentgrep.com/patent/US20140197462A1

## CPC

- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

There are disclosed herein various implementations of semiconductor structures including high resistivity substrates. In one exemplary implementation, such a semiconductor structure includes a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm), and a III-N high electron mobility transistor (HEMT) having a drain, a source, and a gate, fabricated over the substrate. The III-N HEMT is configured to produce a two-dimensional electron gas (2 DEG). The resistivity of the substrate reduces the capacitive coupling of the 2 DEG to the substrate. In one implementations, a spatially confined dielectric region is formed in the substrate, under at least one of the drain and the source.

## Claims

### Claim 1

A semiconductor structure comprising:
a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm);
a III-N high electron mobility transistor (HEMT) including a source, a drain, and a gate, fabricated over said substrate, said III-N HEMT configured to produce a two-dimensional electron gas (2 DEG);
a spatially confined dielectric region formed in said substrate, under at least one of said drain and said source.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 10 kΩ-cm.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 50 kΩ-cm.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein said substrate comprises a group IV substrate.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein said substrate comprises a silicon substrate.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein said spatially confined dielectric region is substantially centered under said at least one of said drain and said source.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein all sides of said spatially confined dielectric region are surrounded by said substrate.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein a top side of said spatially confined dielectric region is not covered by said substrate.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein said spatially confined dielectric region comprises silicon oxide.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein said substrate comprises a first substrate layer having said spatially confined dielectric region formed therein, and a second substrate layer situated over said first substrate layer and under said III-N HEMT.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein said substrate comprises a plurality of said spatially confined dielectric regions.

### Claim 12

A semiconductor structure comprising:
a substrate having a resistivity of greater than or approximately equal to one kiloohm-centimeter (1 kΩ-cm);
a group III-N high electron mobility transistor (HEMT) including a source, a drain, and a gate, fabricated over said substrate;
a spatially confined dielectric region formed in said substrate, under at least one of said drain and said source;
said resistivity of said substrate and said spatially confined dielectric reducing a capacitive coupling of said at least one of said drain and said source to said substrate.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 10 kΩ-cm.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, wherein said resistivity of said substrate is in a range from approximately 1 kΩ-cm to approximately 50 kΩ-cm.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, wherein said substrate comprises a group IV substrate.

### Claim 16 (depends on 12)

The semiconductor structure of claim 12, wherein said spatially confined dielectric region is substantially centered under said at least one of said drain and said source.

### Claim 17 (depends on 12)

The semiconductor structure of claim 12, wherein all sides of said spatially confined dielectric region are surrounded by said substrate.

### Claim 18 (depends on 12)

The semiconductor structure of claim 12, wherein a top side of said spatially confined dielectric region is not covered by said substrate.

### Claim 19 (depends on 12)

The semiconductor structure of claim 12, wherein said spatially confined dielectric region comprises silicon oxide.

### Claim 20 (depends on 12)

The semiconductor structure of claim 12, wherein said substrate comprises a first substrate layer having said spatially confined dielectric region formed therein, and a second substrate layer situated over said first substrate layer and under said III-N HEMT.