# US 2014/0197461 A1 · Semiconductor Structure Including A Spatially Confined Dielectric Region

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- Number: US 2014/0197461 A1
- Document ID: US20140197461A1
- Status: Published application
- Kind: A1
- Application number: 14/140,222
- Filed: 2013-12-24
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: International Rectifier Corporation
- Applicants: International Rectifier Corporation
- Inventors: Michael A. Briere
- Web page: https://patentgrep.com/patent/US20140197461A1

## CPC

- H10W 10/10: Isolation regions comprising dielectric materials
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

There are disclosed herein various implementations of semiconductor structures including one or more spatially confined dielectric regions. In one exemplary implementation, such a semiconductor structure includes a III-Nitride field-effect transistor (FET) having a drain, a source, and a gate, fabricated over a substrate. A spatially confined dielectric region is formed under the drain in the substrate, the spatially confined dielectric region reducing a capacitive coupling of the drain to the substrate. In another exemplary implementation, a spatially confined dielectric region is formed under each of the source and the drain of the FET, in the substrate, the spatially confined dielectric regions reducing a capacitive coupling of the source and the drain to the substrate.

## Claims

### Claim 1

A semiconductor structure comprising:
a III-Nitride field-effect transistor (FET) including a drain, a source, and a gate, fabricated over a substrate;
a spatially confined dielectric region formed under said drain in said substrate;
said spatially confined dielectric region reducing a capacitive coupling of said drain to said substrate.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein said spatially confined dielectric region is substantially centered under said drain.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein said spatially confined dielectric region comprises silicon oxide.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein said substrate comprises a group IV semiconductor substrate.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein said substrate is one of a silicon substrate and a composite silicon substrate.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein said III-Nitride FET comprises a III-Nitride high electron mobility transistor (HEMT).

### Claim 7

A semiconductor structure comprising:
a III-Nitride field-effect transistor (FET) including a drain, a source, and a gate, fabricated over a substrate;
a spatially confined dielectric region formed under each of said source and said drain in said substrate;
said spatially confined dielectric region reducing a capacitive coupling of said source and said drain to said substrate.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein all sides of said spatially confined dielectric region are surrounded by said substrate.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, wherein a top side of said spatially confined dielectric region is not covered by said substrate.

### Claim 10

A method comprising:
forming a spatially confined dielectric region in a substrate;
fabricating a III-Nitride field-effect transistor (FET) over said substrate, said III-Nitride FET including a drain, a source, and a gate;
said drain of said III-Nitride FET being formed over said spatially confined dielectric region so as to reduce a capacitive coupling of said drain to said substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein said spatially confined dielectric region is formed through oxygen implantation of said substrate.

### Claim 12 (depends on 10)

The method of claim 10, further comprising forming a silicon lateral epitaxial overgrowth layer above said spatially confined dielectric region and below said III-Nitride FET.

### Claim 13 (depends on 10)

The method of claim 10, wherein said spatially confined dielectric region is substantially centered under said drain.

### Claim 14 (depends on 10)

The method of claim 10, wherein said substrate comprises a group IV semiconductor substrate.

### Claim 15 (depends on 10)

The method of claim 10, wherein said substrate is one of a silicon substrate and a composite silicon substrate.

### Claim 16

A method comprising:
forming spatially confined dielectric regions in a substrate;
fabricating a III-Nitride field-effect transistor (FET) over said substrate, said III-Nitride FET including a drain, a source, and a gate;
each of said drain and said source of said III-Nitride FET being formed over a respective one of said spatially confined dielectric regions so as to reduce a capacitive coupling of said drain and said source to said substrate.

### Claim 17 (depends on 16)

The method of claim 16, wherein said spatially confined dielectric regions are formed through oxygen implantation of said substrate.

### Claim 18 (depends on 16)

The method of claim 16, further comprising forming a silicon lateral epitaxial overgrowth layer above said spatially confined dielectric regions and below said III-Nitride FET.

### Claim 19 (depends on 16)

The method of claim 16, wherein said substrate comprises a group IV semiconductor substrate.

### Claim 20 (depends on 16)

The method of claim 16, wherein said substrate is one of a silicon substrate and a composite silicon substrate.