# US 2014/0197459 A1 · Semiconductor device

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- Number: US 2014/0197459 A1
- Document ID: US20140197459A1
- Status: Published application
- Kind: A1
- Application number: 13/976,757
- Filed: 2012-01-04
- Published: 2014-07-17
- Earliest claimed: 2011-01-04
- Assignees: Ecole Polytechnique Federale De Lausanne (Epfl)
- Inventors: Andras Kis; Branimir Radisavljevic
- Web page: https://patentgrep.com/patent/US20140197459A1

## CPC

- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 64/033: {comprising ferroelectric layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor device comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS2, MoSe2, WS2, WSe2, MoTe2 or WTe2.

## Claims

### Claim 1

Semiconductor device comprising a source electrode, a drain electrode and a semiconducting layer consisting of a single or double 2-dimensional layer(s) made from one of the following materials: MoS2, MoSe2, WS2, WSe2, MoTe2 or WTe2.

### Claim 2 (depends on 1)

Semiconductor device according to claim 1 furthermore comprising a gate electrode and a dielectric layer placed between said semiconducting layer and the gate electrode, said dielectric layer being configured to protect the semiconducting layer from the environment and increase its mobility.

### Claim 3 (depends on 2)

Semiconductor device according to claim 2 wherein said gate electrode is extending over said source electrode and said drain electrode.

### Claim 4 (depends on 2)

Semiconductor device according to claim 2 wherein said gate electrode is embedded within said dielectric layer.

### Claim 5 (depends on 1)

Semiconductor device according to claim 1 devoid of a top gate electrode and a top dielectric layer.

### Claim 6 (depends on 5)

Sensor based on a semiconductor device according to claim 5.

### Claim 7 (depends on 2)

Semiconductor device according to claim 2 comprising a second gate electrode.

### Claim 8 (depends on 7)

Semiconductor device according to claim 7 wherein said second gate electrode is embedded within an oxide layer.

### Claim 9 (depends on 1)

Semiconductor device according to claim 1, wherein said semiconducting layer is consisting of a single 2-dimensional layer.

### Claim 10 (depends on 1)

Semiconductor device according to claim 1, wherein said semiconducting layer is a nanosized layer.

### Claim 11 (depends on 10)

Semiconductor device according to claim 10 wherein said semiconducting layer is between 0.5 and 1.5 nm thick.

### Claim 12 (depends on 1)

Semiconductor device according to claim 1, wherein at least one of said electrodes is made of graphene.

### Claim 13 (depends on 1)

Semiconductor device according to claim 1, wherein said dielectric layer is made of HfO2.

### Claim 14 (depends on 1)

Transistor comprising a semiconductor device according to claim 1.

### Claim 15 (depends on 1)

Digital inverter comprising a semiconductor device according to claim 1.