# US 2014/0197458 A1 · FinFET Device and Method of Fabricating Same

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- Number: US 2014/0197458 A1
- Document ID: US20140197458A1
- Status: Published application
- Kind: A1
- Application number: 14/017,036
- Filed: 2013-09-03
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Ching; Jiun-Jia Huang; Chao-Hsiung Wang; Chi-Wen Liu
- Web page: https://patentgrep.com/patent/US20140197458A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/798: {being provided in or under the channel regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

## Claims

### Claim 1

An integrated circuit structure comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate, wherein the isolation regions comprise opposite sidewalls facing each other; and
a fin structure comprising:
a silicon fin higher than top surfaces of the isolation regions;
a germanium-containing semiconductor region overlapped by the silicon fin;
silicon oxide regions on opposite sides of the germanium-containing semiconductor region; and
a first germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the silicon oxide regions are separated from each other by the germanium-containing semiconductor region.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the silicon oxide regions are portions of a continuous silicon oxide region, and wherein the continuous silicon oxide region further comprises portions overlying and underlying the germanium-containing semiconductor region.

### Claim 4 (depends on 3)

The integrated circuit structure of claim 3, wherein one of the germanium-containing semiconductor region and the first germanium-containing semiconductor layer is a substantially pure germanium region.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1 further comprises:
a silicon strip between the opposite sidewalls of the isolation regions, wherein sidewalls of the silicon strip are in contact with the opposite sidewalls of the isolation regions, and wherein the silicon strip is overlapped by the germanium-containing semiconductor region, portions of the silicon oxide regions, and portions of the first germanium-containing semiconductor layer; and
a second germanium-containing semiconductor layer between and in contact with the silicon strip and one of the silicon oxide regions.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, wherein at least a portion of the silicon oxide regions is over the top surfaces of the isolation regions.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1 further comprising:
a gate stack on sidewalls and a top surface of the silicon fin; and
source/drain regions on opposite sides of the silicon fin.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7, wherein the gate stack is in contact with sidewalls of the silicon oxide regions.

### Claim 9

An integrated circuit structure comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate, wherein the isolation regions comprise opposite sidewalls facing each other; and
a fin structure comprising:
a silicon fin higher than top surfaces of the isolation regions;
a silicon strip between the opposite sidewalls of the isolation regions, wherein sidewalls of the silicon strip are in contact with the opposite sidewalls of the isolation regions;
a germanium-containing semiconductor region between aligned to the silicon fin and the silicon strip;
a first and a second silicon oxide region on opposite sides of the germanium-containing semiconductor region;
a first germanium-containing semiconductor layer between and in contact with the silicon fin and the first silicon oxide region;
a second germanium-containing semiconductor layer between and in contact with the silicon fin and the second silicon oxide region;
a third germanium-containing semiconductor layer between and in contact with the silicon strip and the first silicon oxide region; and
a fourth germanium-containing semiconductor layer between and in contact with the silicon strip and the second silicon oxide region.

### Claim 10 (depends on 9)

The integrated circuit structure of claim 9, wherein the germanium-containing semiconductor region has a gradient germanium percentage, with inner portions of the germanium-containing semiconductor region having lower germanium percentages than respective outer portions.

### Claim 11 (depends on 9)

The integrated circuit structure of claim 9, wherein at least a portion of the first silicon oxide region is over the top surfaces of the isolation region.

### Claim 12 (depends on 9)

The integrated circuit structure of claim 9, wherein the silicon fin and the silicon strip are free from germanium.

### Claim 13 (depends on 9)

The integrated circuit structure of claim 9, wherein each of the first and the second oxide regions comprises a portion not overlapped by the silicon fin.

### Claim 14 (depends on 9)

The integrated circuit structure of claim 9, wherein the first and the second oxide regions are fully disconnected from each other.

### Claim 15 (depends on 9)

The integrated circuit structure of claim 9 further comprising:
a gate stack on sidewalls and a top surface of the silicon fin; and
source/drain regions on opposite sides of the silicon fin.

### Claim 16 (depends on 15)

The integrated circuit structure of claim 15, wherein the gate stack is in contact with sidewalls of the first and the second silicon oxide regions.

### Claim 17

An integrated circuit structure comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate, wherein the isolation regions comprise opposite sidewalls facing each other; and
a fin structure comprising:
a silicon fin higher than top surfaces of the isolation regions;
a germanium-containing semiconductor region; and
a silicon oxide region comprising:
a first and a second portion on opposite sides of the germanium-containing semiconductor region; and
a top portion connecting the first portion to the second portion, wherein the top portion fully separates the germanium-containing semiconductor region from the silicon fin.

### Claim 18 (depends on 17)

The integrated circuit structure of claim 17 further comprising:
a silicon strip between the opposite sidewalls of the isolation regions, wherein sidewalls of the silicon strip are in contact with the opposite sidewalls of the isolation regions;
a bottom portion of the silicon oxide region connecting the first portion to the second portion of the oxide region, wherein the bottom portion fully separates the germanium-containing semiconductor region from the silicon strip; and
a germanium-containing semiconductor layer between and in contact with the silicon strip and the bottom portion of the silicon oxide region.

### Claim 19 (depends on 17)

The integrated circuit structure of claim 17 further comprising:
a germanium-containing semiconductor layer between and in contact with the silicon fin and the top portion of the silicon oxide region.

### Claim 20 (depends on 17)

The integrated circuit structure of claim 17, wherein the germanium-containing semiconductor region is formed of substantially pure germanium.