# US 2014/0197457 A1 · FinFET Device and Method of Fabricating Same

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- Number: US 2014/0197457 A1
- Document ID: US20140197457A1
- Status: Published application
- Kind: A1
- Application number: 13/902,322
- Filed: 2013-05-24
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Chih-Hao Wang; Kuo-Cheng Ching; Gwan Sin Chang; Zhiqiang Wu
- Web page: https://patentgrep.com/patent/US20140197457A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 64/0135: {by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/242: {of Group IV materials}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having a gate region and source and drain (S/D) regions;
a first fin structure in the gate region, the first fin structure including:
a first semiconductor material layer as a lower portion of the first fin structure;
a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure;
a first semiconductor material layer as a center portion of the middle portion of the first fin structure; and
a second semiconductor material layer as an upper portion of the first fin structure;
a high-k (HK)/metal gate (MG) stack in the gate region, the HK/MG stack wrapping over a portion of the first fin structure; and
S/D features in the S/D region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor material layer includes epitaxially grown silicon germanium (SiGex), where x is Ge composition in atomic percent.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein in the gate region, the SiGe layer of the center portion of the middle portion has a higher Ge composition x than the SiGe layer of the lower portion of the of the first fin structure.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the Ge composition x of the SiGe layer of the center portion of the middle portion is in a range of about 0.2 to about 0.5.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein SiGex layer has a thickness in a range of about 5 nm to about 40 nm.

### Claim 6 (depends on 2)

The semiconductor device of claim 2, wherein the outer portion of the middle portion of the first fin structure is SiGeOy, where y is oxygen composition in atomic percent.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein SiGeOy is formed by performing a thermal oxidation process to the SiGex layer in the first fin in the gate region, with volume expansion.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor material includes silicon (Si).

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the Si layer has a thickness in a range of about 20 nm to about 50 nm.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the S/D features include an expitaxially grown semiconductor material.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein between two adjacent isolation regions, there is a single source feature, a single drain feature, and multiple HK/MG stacks.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the single S/D features serve as a common source/drain for the multiple HK/MG stacks.

### Claim 13

A semiconductor device comprising:
a substrate having a plurality of isolation regions, a gate region between adjacent isolation regions, and source and drain regions separated by the gate region;
a first fin structure in a gate region, the first fin structure including:
a silicon germanium (SiGex) layer as a lower portion, where x is Ge composition in atomic percent;
a silicon germanium oxide (SiGeOy) layer as an middle-outer portion, where y is oxygen composition in atomic percent;
a SiGez layer as a middle-center portion, where z is Ge composition in atomic percent; and
a Si layer as an upper portion;
source and drain features in the source and drain regions, respectively; and
a high-k/metal gate (HK/MG) in the gate region, wrapping over a portion of the first fin structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein z is substantially higher than x.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein SiGeOy is formed by performing a thermal oxidation process to the SiGex layer in the first fin in the gate region, with volume expansion.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein single source and drain features and multiple HK/MG stacks are between two adjacent isolation regions, and wherein the single S/D features serve as a common source/drain for the multiple HK/MG stacks.

### Claim 17

A method for fabricating a fin field-effect transistor (FinFET) device, the method comprising:
providing a substrate, the substrate including:
first fins having a gate region;
source and drain regions separated by the gate region;
intra-isolation regions between the first fins; and
isolation regions containing multiple intra isolation regions.
recessing the first fins;
epitaxially growing a first semiconductor material layer on the recessed first fins;
epitaxially growing a second semiconductor material on top of the first semiconductor material layer;
recessing the intra-isolation region to laterally expose an upper portion of the second semiconductor material to form second fins;
forming a dummy gate stack over the substrate, including wrapping over a first portion of the second fins in the gate region;
removing a second portion of the second fins, the second portion being adjacent the dummy gate stack in the source and drain regions;
epitaxially growing a third semiconductor material on the recessed second fins to form a single source/drain feature between two adjacent isolation regions;
removing the dummy gate stack to form a gate trench;
recessing the intra-isolation regions in the gate trench to laterally exposed a portion of the first semiconductor material in the second fins;
applying a thermal oxidation process to the first and second semiconductor material layers of the second fin in the gate trench to convert an outer portion of the exposed first semiconductor material to a first semiconductor oxide and outer layer of the second semiconductor to a second semiconductor oxide;
removing the second semiconductor oxide to reveal the second semiconductor material as the upper portion of the second fin in the gate trench; and
forming a high-k/metal gate (HK/MG) stack, wrapping over a portion of the second fin.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first semiconductor material is silicon germanium (SiGex), where x is Ge composition in atomic percent, which is in a range of about 0.2 to about 0.5, and the second semiconductor material includes silicon (Si).

### Claim 19 (depends on 17)

The method of claim 17, wherein the thermal oxidation process is conducted in a combination of steam ambient and oxygen ambient with a pressure of about one atmospheric pressure and a temperature in a range of about 400° C. to about 600° C.

### Claim 20 (depends on 17)

The method of claim 17, wherein the single S/D feature serves as a common source/drain for multiple HK/MG stacks between adjacent isolation regions.