# US 2014/0197456 A1 · Semiconductor Device and Fabricating the Same

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- Number: US 2014/0197456 A1
- Document ID: US20140197456A1
- Status: Published application
- Kind: A1
- Application number: 13/740,373
- Filed: 2013-01-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Hao Wang; Kuo-Cheng Ching; Gwan Sin Chang; Zhiqiang Wu
- Web page: https://patentgrep.com/patent/US20140197456A1

## CPC

- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having an N-type field-effect transistor (N-FET) region;
a gate region in the N-FET region;
source and drain (S/D) regions separated by the gate region in the N-FET region;
a first fin structure in the gate region in the N-FET region, the first fin structure including:
a first semiconductor material layer as a lower portion of the first fin structure;
a semiconductor oxide layer as a middle portion of the first fin structure; and
a second semiconductor material layer as an upper portion of the first fin structure;
a second fin structure in S/D regions in the N-FET region, the second fin structure including:
the first semiconductor material layer as a lower portion of the second fin structure;
the semiconductor oxide layer as a first middle portion of the second fin structure, wherein first middle portion of the second fin directly contacts the middle portion of the first fin in the gate region;
the first semiconductor material layer as a second middle portion beside the first middle portion of the second fin structure; and
the second semiconductor material layer as an upper portion of the second fin structure;
source/drain features on top of the upper portion of the second fin structure in the source/drain region; and
a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor material has a larger volume expansion than the second semiconductor material in a thermal oxidation process in oxygen ambient.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the thermal oxidation process is conducted in a combination of steam ambient and oxygen ambient.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the first semiconductor material includes an epitaxial growth silicon germanium (SiGex), where x is Ge composition in atomic percent.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein x is selected to meet a predetermined target of volume expansion during the thermal oxidation process

### Claim 6 (depends on 2)

The semiconductor device of claim 2, wherein the second semiconductor material includes silicon (Si).

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor oxide material is an oxide of the first semiconductor material with a depth (D).

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the semiconductor oxide material includes SiGeOy, where y is oxygen composition in atomic percent.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first middle portion of the second fin structure is an extension of the middle portion of the first fin structure in the gate region, with an extension depth (d).

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first middle portion of the second fin structure includes SiGeOy.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the second middle portion of the second fin includes SiGex.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the upper portion of the second fin includes Si.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the S/D feature includes an expitaxially growth semiconductor material.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the middle portion of the first fin includes the first semiconductor material being wrapped by the first semiconductor oxide.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the first fin structure is a omega-shape, which including:
a first semiconductor material layer as a lower portion of the first fin structure;
a semiconductor oxide layer as a middle portion of the first fin structure with a first width; and
a second semiconductor material layer as an upper portion of the first fin structure with a second width, which is substantially smaller than the first width.

### Claim 16

A semiconductor device comprising:
a substrate having an N-type field-effect transistor (N-FET) region;
a gate region in the N-FET region;
source and drain regions separated by the gate region in the N-FET region;
a first fin structure in a gate region in the N-FET region, the first fin structure including:
a silicon germanium (SiGex) layer as a lower portion, where x is Ge composition in atomic percent;
a silicon germanium oxide (SiGeOy) layer as a middle, where y is oxygen composition in atomic percent; and
a Si layer as an upper portion;
a second fin structure in S/D regions in the N-FET region, the second fin structure including;
the SiGex layer as a lower portion;
the SiGeOy as a first middle portion, wherein it directly contacting the middle portion of the first fin in the gate region;
the SiGex as a second middle portion beside the first middle; and
the Si layer as an upper portion;
source/drain features on top of the upper portion of the second fin structure in the source and drain regions; and
a high-k/metal gate (HKMG) on the substrate including wrapping over a portion of the first fin structure.

### Claim at position 17

17-20. (canceled)

### Claim 21

A semiconductor device comprising:
a first fin structure including: a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as a middle portion of the first fin structure, and a second semiconductor material layer as an upper portion of the first fin structure; and
a second fin structure including: the first semiconductor material layer as a lower portion of the second fin structure, the semiconductor oxide layer as a first middle portion of the second fin structure, the first semiconductor material layer as a second middle portion beside the first middle portion of the second fin structure, and the second semiconductor material layer as an upper portion of the second fin structure.

### Claim 22 (depends on 21)

The device of claim 21, further comprising:
a high-k (HK)/metal gate (MG) stack on the substrate wrapping over a portion of the first fin structure in the gate region.

### Claim 23 (depends on 21)

The device of claim 21, wherein the first semiconductor material includes silicon germanium (SiGe) and the second semiconductor material includes silicon.

### Claim 24 (depends on 21)

The device of claim 21, further comprising:
source/drain features on top of the upper portion of the second fin structure in the source/drain region.