# US 2014/0197455 A1 · Semiconductor substructure having elevated strain material-sidewall interface and method of making the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0197455 A1
- Document ID: US20140197455A1
- Status: Published application
- Kind: A1
- Application number: 13/739,010
- Filed: 2013-01-11
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Yang LEE; Yuan-Ching PENG; Chun-Hsiung TSAI
- Web page: https://patentgrep.com/patent/US20140197455A1

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.

## Claims

### Claim 1

A semiconductor substructure comprising:
a substrate, having an upper surface;
a gate structure formed over said substrate;
a spacer formed along a sidewall of said gate structure; and
a source/drain structure disposed adjacent said gate structure, said source/drain structures formed of a strain material and disposed in an recess that extends below said upper surface of said substrate,
wherein an interface is provided between said spacer and said source-drain structure above said upper surface of said substrate.

### Claim 2 (depends on 1)

The semiconductor substructure as in claim 1, wherein said semiconductor substructure comprises a PMOS transistor.

### Claim 3 (depends on 1)

The semiconductor substructure as in claim 1, wherein said strain material comprises SiGe.

### Claim 4 (depends on 1)

The semiconductor substructure as in claim 1, wherein said substrate comprises crystalline silicon.

### Claim 5 (depends on 1)

The semiconductor substructure as in claim 1, further comprising a P-type dopant impurity region in said source-drain structure, said gate structure, or both.

### Claim 6 (depends on 1)

The semiconductor substructure as in claim 1, wherein said gate structure comprises a gate electrode and a gate dielectric, and said spacer contacts said gate structure.

### Claim 7 (depends on 1)

The semiconductor substructure as in claim 1, further comprising at least one nitride layer between said spacer and said gate structure.

### Claim 8 (depends on 1)

The semiconductor substructure as in claim 1, wherein said spacer comprises a nitride.

### Claim 9 (depends on 1)

A semiconductor substructure as in claim 1, further comprising:
a second spacer formed along a second sidewall of said gate structure opposite said sidewall; and
a second source/drain structure disposed adjacent said gate structure opposite said source/drain structure, said second source/drain structures formed of a strain material and disposed in a second recess that extends below said upper surface of said substrate,
wherein a second interface between said second spacer and said second source-drain structure is at least 2 nm above said upper surface of said substrate.

### Claim 10 (depends on 1)

A semiconductor substructure as in claim 1, wherein the interface is at least 1 nm above said upper surface of said substrate.

### Claim 11

A method for forming a semiconductor substructure, said method comprising:
providing a semiconductor substrate;
forming a gate structure over said crystalline silicon material;
forming a spacer along a sidewall of said gate structure;
creating an recess extending into said semiconductor substrate, adjacent said gate structure; and
filling said recess with a strain material, said strain material forming an interface with said spacer, wherein said interface is above an upper surface of said semiconductor substrate.

### Claim 12 (depends on 11)

The method as in claim 11, wherein said creating recesses comprises anisotropic etching where said recesses extend under said spacer.

### Claim 13 (depends on 11)

The method as in claim 11, further comprising:
forming an insertion layer on said semiconductor substrate, wherein said spacer is formed on said insertion layer, and
removing said insertion layer under said spacer prior to said filing step.

### Claim 14 (depends on 13)

The method as in claim 13, wherein said insertion layer comprises an oxide and said spacer comprises a nitride.

### Claim 15 (depends on 11)

The method as in claim 11, further comprising,
replacing said gate structure with a high dielectric (K), metal gate.

### Claim 16 (depends on 11)

The method as in claim 11, wherein said spacer comprises a nitride.

### Claim 17 (depends on 11)

The method as in claim 11, further comprising:
forming a nitride layer along said sidewall of said gate structure prior to said step of forming said spacer.

### Claim 18 (depends on 17)

The method as in claim 17, further comprising,
replacing said gate structure with a high dielectric (K), metal gate.

### Claim 19 (depends on 11)

The method as in claim 11, wherein:
said forming a spacer step, comprises forming a second spacer along a second sidewall of said gate structure opposite said sidewall;
said creating an recess step, comprises creating a second recess extending into said semiconductor substrate, adjacent said gate structure and opposite said recess; and
said filling an recess step, comprises filling said second recess with a strain material, said strain material forming a second interface with said second spacer, wherein said second interface is above an upper surface of said semiconductor substrate.

### Claim 20

A method for forming a semiconductor substructure, said method comprising:
providing a semiconductor substrate;
forming a gate structure over said crystalline silicon material;
forming an insertion layer on said semiconductor substrate;
forming a spacer along a sidewall of said gate structure, wherein said spacer is formed over said insertion layer;
creating at least one recess adjacent said gate structure, said recesses extending into said semiconductor substrate and extending under said spacer;
removing a portion of said insertion layer under said spacer prior to said filing step; and
filling said at least recess with a strain material, said strain material forming an interface with said spacer, wherein said interface is at least 2 nm above an upper surface of said semiconductor substrate.