# US 2014/0197448 A1 · Bidirectional Semiconductor Device for Protection against Electrostatic Discharges > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197448 A1 - Document ID: US20140197448A1 - Status: Published application - Kind: A1 - Application number: 14/155,891 - Filed: 2014-01-15 - Published: 2014-07-17 - Earliest claimed: 2013-01-15 - Assignees: STMicroelectronics S.r.l. - Applicants: STMicroelectronics SA - Inventors: Philippe Galy; Johan Bourgeat - Web page: https://patentgrep.com/patent/US20140197448A1 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes - H10D 18/80: Bidirectional devices, e.g. triacs - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device} - H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology. ## Claims ### Claim 1 An integrated circuit produced on a bulk semiconductor substrate in a given CMOS technology, the integrated circuit comprising: a component produced in the CMOS technology and having at least one MOS transistor; a protective semiconductor device configured to protect the component against electrostatic discharges, the protection device comprising a doublet including two floating-gate thyristors coupled in parallel and head-to-tail, each thyristor having two electrode regions, the thyristors respectively having two separate gates and a common semiconductor gate region; wherein a product of current gains of transistors of each thyristor are greater than 1; and wherein an intrinsic triggering voltage of the protective semiconductor device is less than a breakdown voltage of the at least one MOS transistor of the component. ### Claim 2 (depends on 1) The integrated circuit according to claim 1, wherein each electrode region of the at least one of the thyristors has a dimension measured perpendicularly to a spacing direction of the two electrodes, the dimension being adjusted so as to impart the intrinsic triggering voltage that is less than the breakdown voltage of the at least one MOS transistor of the component. ### Claim 3 (depends on 1) The integrated circuit according to claim 1, wherein each electrode region of the two thyristors has a dimension measured perpendicularly to a spacing direction of the two electrodes, the dimension being adjusted so as to impart to the two thyristors respective intrinsic triggering voltages that less than the breakdown voltage of the at least one MOS transistor of the component. ### Claim 4 (depends on 3) The integrated circuit according to claim 3, wherein the dimension of the electrode regions of one of the thyristors is different from the dimension of the electrode regions of the other thyristor. ### Claim 5 (depends on 1) The integrated circuit according to claim 1, wherein the CMOS technology comprises a 28 nm CMOS technology and wherein the dimension is greater than 6 microns. ### Claim 6 (depends on 1) The integrated circuit according to claim 1, wherein the CMOS technology comprises a 32 nm CMOS technology and wherein the dimension is greater than 6 microns. ### Claim 7 (depends on 1) The integrated circuit according to claim 1, wherein a dimension of the common gate region, measured parallel to the spacing direction, is greater than a minimum dimension defined by design rules of the CMOS technology. ### Claim 8 (depends on 7) The integrated circuit according to claim 7, wherein the common gate region comprises a zone having the same conductivity type as the common gate region but doped more heavily than the common gate region. ### Claim 9 (depends on 7) The integrated circuit according to claim 7, wherein the common gate region comprises a zone having an opposite conductivity type to the common gate region. ### Claim 10 (depends on 9) The integrated circuit according to claim 9, wherein the zone of the common gate is doped more heavily than the common gate region. ### Claim 11 (depends on 7) The integrated circuit according to claim 7, wherein the common gate region comprises an electrically insulating region. ### Claim 12 An integrated circuit produced in a given CMOS technology, the integrated circuit comprising: a protective semiconductor device having a doublet including two floating-gate thyristors coupled in parallel and head-to-tail, each thyristor having a pair of electrode regions, the two thyristors respectively having two separate gates and a common semiconductor gate region having a dimension, measured parallel to a spacing direction of the electrodes of each pair, greater than a minimum dimension defined by design rules of the technology. ### Claim 13 (depends on 12) The integrated circuit according to claim 12, wherein the common gate region comprises a zone having the same conductivity type as the common gate region but doped more heavily than the common gate region. ### Claim 14 (depends on 12) The integrated circuit according to claim 12, wherein the common gate region comprises a zone having an opposite conductivity type to the common gate region. ### Claim 15 (depends on 14) The integrated circuit according to claim 14, wherein the zone of the common gate is doped more heavily than the common gate region. ### Claim 16 (depends on 12) The integrated circuit according to claim 12, wherein the common gate region comprises an electrically insulating region. ### Claim 17 (depends on 12) The integrated circuit according to claim 12, wherein the common gate region comprises at least one zone selected from the group consisting of a zone having the same conductivity type as the common gate region but doped more heavily than the common gate region, a zone having the opposite conductivity type to the common gate region and an electrically insulating region. ### Claim 18 (depends on 17) The integrated circuit according to claim 17, wherein the common gate region comprises three zones selected from the group, with two identical zones surrounding a different zone. ### Claim 19 (depends on 12) The integrated circuit according to claim 12, wherein the integrated circuit is a produced on a bulk semiconductor substrate. ### Claim 20 A method of making an integrated circuit, the method comprising: designing a protective semiconductor device having a doublet including two floating-gate thyristors coupled in parallel and head-to-tail, each thyristor having two electrode regions, the two thyristors respectively having two separate gates and a common semiconductor gate region, a product of current gains of two transistors of each thyristor being greater than 1, wherein each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to a spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than a breakdown voltage of a transistor fabricated in a selected CMOS technology; and fabricating an integrated circuit in a semiconductor body, the integrated circuit including the protective semiconductor device as designed and a plurality of transistors fabricated in the selected CMOS technology. ### Claim 21 (depends on 20) The method according to claim 20, wherein each electrode region of the at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart an intrinsic triggering voltage less than the breakdown voltage of the transistor fabricated in the selected CMOS technology. ### Claim 22 (depends on 20) The method according to claim 20, wherein each electrode region of the two thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the two thyristors respective intrinsic triggering voltages less than the breakdown voltage of the transistor fabricated in the selected CMOS technology. ### Claim 23 (depends on 22) The method according to claim 22, wherein the dimension of the electrode regions of one of the thyristors is different from the dimension of the electrode regions of the other thyristor. ### Claim 24 (depends on 20) The method according to claim 20, wherein the CMOS technology comprises a 28 nm CMOS technology and wherein the dimension is greater than 6 microns. ### Claim 25 (depends on 20) The method according to claim 20, wherein the CMOS technology comprises a 32 nm CMOS technology and wherein the dimension is greater than 6 microns. ### Claim 26 (depends on 20) The method according to claim 20, wherein a dimension of the common gate region, measured parallel to the spacing direction, is greater than the minimum dimension defined by design rules of the CMOS technology.