# US 2014/0197418 A1 · Semiconductor structure having sets of iii-v compound layers and method of forming the same

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- Number: US 2014/0197418 A1
- Document ID: US20140197418A1
- Status: Published application
- Kind: A1
- Application number: 13/743,045
- Filed: 2013-01-16
- Published: 2014-07-17
- Earliest claimed: 2013-01-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chi-Ming CHEN; Po-Chun LIU; Chung-Yi YU; Chia-Shiung TSAI
- Web page: https://patentgrep.com/patent/US20140197418A1

## CPC

- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/8171: {Doping structures, e.g. doping superlattices or nipi superlattices}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 14/3216: {Nitrides}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3254: {Graded layers}
- H10P 14/3416: {Nitrides}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a first III-V compound layer over the substrate, the first III-V compound layer having a first type doping;
one or more sets of III-V compound layers over the first III-V compound layer, each of the one or more sets of III-V compound layers comprising a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer, the upper III-V compound layer having the first type doping, and the lower III-V compound layer being at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping;
a second III-V compound layer over the one or more sets of III-V compound layers, the second III-V compound layer being either undoped or unintentionally doped having the second type doping; and
an active layer over the second III-V compound layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first type doping is P-type doping, and the second type doping is N-type doping.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the first type doping is implemented by dopants including carbon, iron, magnesium, or zinc.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein the second type doping is implemented by dopants including silicon or oxygen.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein, when a layer over the first III-V compound layer is configured to cause a depletion region formed within the first III-V compound layer, the first III-V compound layer has a thickness sufficient to prevent the depletion region from extending through the entire thickness of the first III-V compound layer.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein
the first III-V compound layer has a thickness greater than 0.15 μm, and
the first III-V compound layer has a doping concentration greater than 1.0×1019 atoms/cm3.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein an upper III-V compound layer of one of the one or more sets of III-V compound layers has a thickness sufficient to prevent a depletion region from extending through the entire thickness of the upper III-V compound layer when a layer over the upper III-V compound layer is configured to cause the depletion region formed within the upper III-V compound layer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the upper III-V compound layer of the one of the one or more sets of III-V compound layers has a thickness no less than that of the layer immediately on the upper III-V compound layer.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein an upper III-V compound layer of one of the one or more sets of III-V compound layers has a first thickness, a lower III-V compound layer of the one of the one or more sets of III-V compound layers has a second thickness, and the first thickness and the second thickness range from 0.05 μm to 0.1 μm.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein an upper III-V compound layer of one of the one or more sets of III-V compound layers has a doping concentration ranging from 1.0×1015 to 1.0×1019 atoms/cm3.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, a lower III-V compound layer of one of the one or more sets of III-V compound layers has a doping concentration no greater than 1.0×1017 atoms/cm3.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein the first III-V compound layer, the second III-V compound layer, and the one or more sets of III-V compound layers are gallium nitride (GaN) layers.

### Claim 13

A semiconductor structure, comprising:
a substrate;
a graded aluminum gallium nitride (AlGaN) layer over the substrate;
a first gallium nitride (GaN) layer over the AlGaN substrate, the first GaN layer having P-type doping;
one or more sets of GaN layers over the first GaN layer, each of the one or more sets of GaN layers comprising a lower GaN layer and an upper GaN layer on the lower GaN layer, the upper GaN layer having the P-type doping, and the lower GaN layer being at least one of undoped, unintentionally doped having N-type doping, or doped having the N-type doping;
a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping
an active layer over the second GaN layer;
a source electrode over the second GaN layer;
a drain electrode over the second GaN layer; and
a gate electrode between the source electrode and the drain electrode and over the active layer.

### Claim 14 (depends on 14)

The semiconductor structure of claim 14, wherein the active layer comprises AlN or AlGaN.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, further comprising:
a dielectric layer between the gate electrode and the active layer.

### Claim 16 (depends on 13)

The semiconductor structure of claim 13, wherein one of the one or more sets of GaN layers is directly on the first GaN layer, the lower III-V compound layer of the one pair of the one or more sets of GaN layers is configured to cause a depletion region formed within the first GaN layer, and the first GaN layer has a thickness sufficient to prevent the depletion region from extending through the entire thickness of the first GaN layer.

### Claim 17 (depends on 13)

The semiconductor structure of claim 13, wherein an upper GaN of one of the one or more sets of GaN layers has a doping concentration ranging from 1.0×1015 to 1.0×1019 atoms/cm3.

### Claim 18 (depends on 13)

The semiconductor structure of claim 13, wherein a lower GaN layer of one of the one or more sets of GaN layers has a doping concentration no greater than 1.0×1017 atoms/cm3.

### Claim 19

A method of forming a semiconductor structure, the method comprising:
forming a first III-V compound layer having a first-type doping over a substrate;
forming one or more sets of III-V compound layers over the first III-V compound layer, each of the one or more sets of III-V compound layers comprising a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer, the upper III-V compound layer having the first type doping, and the lower III-V compound layer being at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping;
forming a second III-V compound layer over the one or more sets of III-V compound layers, the second III-V compound layer being either undoped or unintentionally doped having the second type doping; and
forming an active layer over the second III-V compound layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the forming the first III-V compound layer, the forming the second III-V compound layer, and the forming the one or more pairs of III-V compound layers are performed by using a metal-organic chemical vapor deposition (MOCVD) process.