# US 2014/0197417 A1 · Method for producing display panel, and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197417 A1 - Document ID: US20140197417A1 - Status: Published application - Kind: A1 - Application number: 14/217,817 - Filed: 2014-03-18 - Published: 2014-07-17 - Earliest claimed: 2011-11-16 - Assignees: Panasonic Corporation - Applicants: Panasonic Corporation - Inventors: Norishige NANAI; Takaaki UKEDA; Akihito MIYAMOTO - Web page: https://patentgrep.com/patent/US20140197417A1 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - H10D 86/021: {of multiple TFTs} - H10D 86/0241: {using liquid deposition, e.g. printing} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10K 59/122: Pixel-defining structures or layers, e.g. banks - H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT] - H10K 59/124: Insulating layers formed between TFT elements and OLED elements - H10K 59/1201: {Manufacture or treatment} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract In a method for producing a display panel, a base substrate having an upper surface on which an electrode is located is prepared. A first layer having a first opening overlapping with the electrode in plan-view is formed on the base substrate. A second layer having a second opening overlapping with the first opening in plan-view is formed on the first layer. The second opening has a smaller area than the first opening in plan-view. A wiring layer is formed in the first opening and the second opening, in contact with the electrode. The second layer includes a portion located on an upper surface of the first layer and a portion located in the first opening. The portion of the second layer located in the first opening covers an internal side surface of the first layer located around the first opening. ## Claims ### Claim 1 A method for producing a display panel, comprising: preparing a base substrate having an upper surface on which an electrode is located; forming a gate insulating film on the base substrate such that the gate insulating film has a first opening therein at a position overlapping with the electrode in plan-view; forming a bank layer on the gate insulating film such that the bank layer has a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and forming a wiring layer in the first opening and the second opening such that the wiring layer is in contact with the electrode, wherein the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening. ### Claim 2 (depends on 1) The method for producing a display panel of claim 1, wherein the first opening has a smaller area than the electrode in plan-view, and a lower surface of the portion of the bank layer in the first opening is in contact with an upper surface of the electrode around an entire perimeter of the first opening in plan-view. ### Claim 3 (depends on 1) The method for producing a display panel of claim 1, wherein in the forming of the bank layer, the bank layer is formed such that the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer. ### Claim 4 (depends on 1) The method for producing a display panel of claim 1, wherein the wiring layer is a source electrode or a drain electrode. ### Claim 5 (depends on 1) The method for producing a display panel of claim 1, wherein the bank layer has a greater tolerance than the gate insulating film against a gas or liquid chemical used after the forming of the bank layer. ### Claim 6 A display panel comprising: a base substrate; an electrode located on an upper surface of the base substrate; a gate insulating film located on the base substrate and having a first opening therein at a position overlapping with the electrode in plan-view; a bank layer located on the gate insulating film and having a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and a wiring layer located in the first opening and the second opening, in contact with the electrode, wherein the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening. ### Claim 7 (depends on 6) The display panel of claim 6, wherein the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer. ### Claim 8 (depends on 6) The display panel of claim 6, wherein the wiring layer is a source electrode or a drain electrode. ### Claim 9 A method for producing a transistor array, comprising: preparing a base substrate having an upper surface on which an electrode is located; forming a gate insulating film on the base substrate such that the gate insulating film has a first opening therein at a position overlapping with the electrode in plan-view; forming a bank layer on the gate insulating film such that the bank layer has a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and forming a wiring layer in the first opening and the second opening such that the wiring layer is in contact with the electrode, wherein the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening. ### Claim 10 (depends on 9) The method for producing a transistor array of claim 9, wherein the first opening has a smaller area than the electrode in plan-view, and a lower surface of the portion of the bank layer in the first opening is in contact with an upper surface of the electrode around an entire perimeter of the first opening in plan-view. ### Claim 11 (depends on 9) The method for producing a transistor array of claim 9, wherein in the forming of the bank layer, the bank layer is formed such that the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer. ### Claim 12 (depends on 9) The method for producing a transistor array of claim 9, wherein the wiring layer is a source electrode or a drain electrode. ### Claim 13 (depends on 9) The method for producing a transistor array of claim 9, wherein the bank layer has a greater tolerance than the gate insulating film against a gas or liquid chemical used after the forming of the bank layer. ### Claim 14 A transistor array comprising: a base substrate; an electrode located on an upper surface of the base substrate; a gate insulating film located on the base substrate and having a first opening therein at a position overlapping with the electrode in plan-view; a bank layer located on the gate insulating film and having a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and a wiring layer located in the first opening and the second opening, in contact with the electrode, wherein the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening. ### Claim 15 (depends on 14) The transistor array of claim 14, wherein the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer. ### Claim 16 (depends on 14) The transistor array of claim 14, wherein the wiring layer is a source electrode or a drain electrode.