# US 2014/0197415 A1 · Thin-film transistor array substrate and method of fabricating the same

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- Number: US 2014/0197415 A1
- Document ID: US20140197415A1
- Status: Published application
- Kind: A1
- Application number: 14/216,189
- Filed: 2014-03-17
- Published: 2014-07-17
- Earliest claimed: 2011-02-01
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Chun-Gi You
- Web page: https://patentgrep.com/patent/US20140197415A1

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin-film transistor (TFT) array substrate comprises: a substrate; an active layer and a capacitor first electrode formed on the substrate; a gate insulating film formed on the substrate, the active layer and the capacitor first electrode; a gate electrode formed on the gate insulating film corresponding to the active layer and a capacitor second electrode formed on the gate insulating film corresponding to the capacitor first electrode; an interlayer insulating film formed on the gate insulating film, the gate electrode, and the capacitor second electrode; and a pixel electrode, a source electrode, and a drain electrode formed on the interlayer insulating film; wherein at least one of the source electrode and the drain electrode is formed on the pixel electrode. A method of fabricating the TFT array substrate is also disclosed.

## Claims

### Claim at position 1

1-13. (canceled)

### Claim 14

A method of fabricating a TFT array substrate, the method comprising the steps of:
forming an active layer and a capacitor first electrode on a substrate;
forming a gate insulating film on the substrate, the active layer and the capacitor first electrode;
forming a gate electrode and a capacitor second electrode on the gate insulating film;
sequentially forming an interlayer insulating film and a conductive film for forming a pixel electrode on the gate insulating film, the gate electrode, and the capacitor second electrode;
forming contact holes which expose predetermined regions of the active layer by etching predetermined regions of the conductive film for forming the pixel electrode, the interlayer insulating film, and the gate insulating film;
forming a conductive film for forming source and drain electrodes on the conductive film for forming the pixel electrode;
forming a first photoresist pattern on the conductive film for forming the source and drain electrodes using a halftone mask; and
forming the source and drain electrodes and the pixel electrode by etching the conductive film for forming the source and drain electrodes and the conductive film for forming the pixel electrode using the first photoresist pattern as an etch mask.

### Claim 15 (depends on 14)

The method of claim 14, wherein the step of forming the first photoresist pattern on the conductive film for forming the source and drain electrodes using the halftone mask comprises forming first sub-photoresist patterns which correspond to the source and drain electrodes, respectively, and a second sub-photoresist pattern which corresponds to the pixel electrode.

### Claim 16 (depends on 15)

The method of claim 15, wherein the step of forming the source and drain electrodes and the pixel electrode by etching the conductive film for forming the source and drain electrodes and the conductive film for forming the pixel electrode using the first photoresist pattern as the etch mask comprises:
etching the conductive film for forming the source and drain electrodes and the conductive film for forming the pixel electrode using the first sub-photoresist patterns and the second sub-photoresist pattern as etch masks;
removing the second sub-photoresist pattern; and
etching the conductive film for forming the source and drain electrodes again using the remaining first sub-photoresist patterns as etch masks.

### Claim 17 (depends on 14)

The method of claim 14, wherein the step of forming the gate electrode and the capacitor second electrode on the gate insulating film comprises:
sequentially forming a first conductive film, a second conductive film, and a third conductive film on the gate insulating film;
forming a second photoresist pattern on the third conductive film using a halftone mask; and
etching the first thru third conductive films using the second photoresist pattern as an etch mask.

### Claim 18 (depends on 17)

The method of claim 17, wherein the step of forming the second photoresist pattern comprises forming a first sub-photoresist pattern which corresponds to the gate electrode and a second sub-photoresist pattern which corresponds to the capacitor second electrode.

### Claim 19 (depends on 18)

The method of claim 18, wherein the step of etching the first thru third conductive films using the second photoresist pattern as the etch mask comprises:
etching the first thru third conductive films using the first sub-photoresist pattern and the second sub-photoresist pattern as etch masks;
removing the second sub-photoresist pattern; and
etching the second conductive film and the third conductive film again using the remaining first sub-photoresist pattern as an etch mask.

### Claim 20 (depends on 14)

A thin-film transistor (TFT) array substrate fabricated by the process of claim 14, comprised of the pixel electrode is formed on the interlayer insulating film in direct contact with the interlayer insulating film.