# US 2014/0197414 A1 · Array substrate and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197414 A1 - Document ID: US20140197414A1 - Status: Published application - Kind: A1 - Application number: 14/104,051 - Filed: 2013-12-12 - Published: 2014-07-17 - Earliest claimed: 2013-01-11 - Assignees: Beijing Boe Optoelectronics Technology Co., Ltd. - Applicants: Beijing Boe Optoelectronics Technology Co., Ltd. - Inventors: Jian GUO - Web page: https://patentgrep.com/patent/US20140197414A1 ## CPC - H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses} - G02F 1/1345: Conductors connecting electrodes to cell terminals - G02F 1/136286: {Wiring, e.g. gate line, drain line} - H10D 86/01: Manufacture or treatment - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract Embodiments of the present invention disclose an array substrate comprising a peripheral wiring area which comprises an electrostatic discharge prevention area. The electrostatic discharge prevention area comprises a substrate on which a gate line, a gate insulating layer, a data line, a protection layer and a transparent electrode are formed. A first through hole is formed in the gate insulating layer, a second through hole is formed at the position of the protection layer corresponding to the first through hole, and the gate line, the data line and the transparent electrode are connected together through the first through hole and the second through hole. The present invention also discloses a manufacturing method of the array substrate. ## Claims ### Claim 1 An array substrate comprising a peripheral wiring area which comprises an electrostatic discharge prevention area, the electrostatic discharge prevention area comprises a substrate, and a gate line, a gate insulating layer, a data line, a protection layer and a transparent electrode formed on the substrate, wherein, a first through hole is formed in the gate insulating layer, a second through hole is formed at a position of the protection layer corresponding to the first through hole, and the gate line, the data line and the transparent electrode are connected together through the first through hole and the second through hole. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein, the transparent electrode comprises a first transparent electrode and a second transparent electrode, a passivation layer is formed between the first transparent electrode and the second transparent electrode, and a third through hole is formed at a position of the passivation layer corresponding to the first through hole. ### Claim 3 (depends on 1) The array substrate according to claim 1, wherein, one of the first transparent electrode and the second transparent electrode located at an upper layer is a slit electrode. ### Claim 4 (depends on 1) The array substrate according to claim 1, wherein, the material of the protection layer is an organic resin. ### Claim 5 (depends on 4) The array substrate according to claim 4, wherein, the organic resin is one of, or a mixture of two of organic resins with Si—C or Si—O as a main chain. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein, the array substrate further comprises a common electrode through hole area which comprises the gate line, the gate insulating layer, a gate line protection layer, the protection layer and the transparent electrode formed on the substrate, wherein, the gate insulating layer is formed with a fourth through hole, the protection layer is formed with a fifth through hole at a position corresponding to the fourth through hole, and the gate line, the gate line protection layer and the transparent electrode are connected together through the fourth through hole and the fifth through hole. ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein, the array substrate further comprises a chip bonding area which comprises the gate insulating layer, the data line, the protection layer and the transparent electrode formed on the substrate, wherein, the protection layer is formed with a seventh through hole through which the data line and the transparent electrode are connected together. ### Claim 8 (depends on 2) The array substrate according to claim 2, wherein, the array substrate further comprises a common electrode through hole area which comprises the gate line, the gate insulating layer, a gate line protection layer, the protection layer and the transparent electrode formed on the substrate, wherein, the gate insulating layer is formed with a fourth through hole, the protection layer is formed with a fifth through hole at a position corresponding to the fourth through hole, and the gate line, the gate line protection layer and the transparent electrode are connected together through the fourth through hole and the fifth through hole. ### Claim 9 (depends on 2) The array substrate according to claim 2, wherein, the array substrate further comprises a chip bonding area which comprises the gate insulating layer, the data line, the protection layer and the transparent electrode formed on the substrate, wherein, the protection layer is formed with a seventh through hole through which the data line and the transparent electrode are connected together. ### Claim 10 A manufacturing method of an array substrate comprising a peripheral wiring area which comprises an electrostatic discharge prevention area, wherein, a step of forming the electrostatic discharge prevention area comprises forming a gate line, a gate insulating layer, a data line, a protection layer and a transparent electrode on a substrate, wherein, the method further comprises: etching a first through hole in the gate insulating layer, etching a second through hole at a position of the protection layer corresponding to the first through hole, so that the gate line, the data line and the transparent electrode are connected together through the first through hole and the second through hole. ### Claim 11 (depends on 10) The method according to claim 10, wherein, the transparent electrode comprises a first transparent electrode and a second transparent electrode; the method further comprises: forming a passivation layer between the first transparent electrode and the second transparent electrode, and etching a third through hole at a position of the passivation layer corresponding to the first through hole. ### Claim 12 (depends on 10) The method according to claim 10, wherein, a material of the protection layer is an organic resin. ### Claim 13 (depends on 12) The method according to claim 12, wherein, the organic resin is one of, or a mixture of two of organic resins with Si—C or Si—O as a main chain. ### Claim 14 (depends on 12) The method according to claim 12, wherein, a step of curing the organic resin is contained when the organic resin is deposited, wherein, a condition for curing the organic resin is baking the organic resin at a temperature above 250° C. and then curing. ### Claim 15 (depends on 12) The method according to claim 12, wherein, a dry etching method is used to etch the organic resin; wherein, the dry etching method is as follow: a1, conducting etching with a mixture gas of SF6, O2 and He at a power of 7000 W-12000 W; and a2, after etching the organic resin part, conducting etching with a mixture gas of SF6 and He at a power of 5000 W-10000 W. ### Claim 16 (depends on 10) The method according to claim 10, wherein, the array substrate further comprises a common electrode through hole area, and a step of forming the common electrode through hole area comprises forming the gate line, the gate insulating layer, a gate line protection layer, the protection layer and the transparent electrode on the substrate, wherein, a fourth through hole is etched in the gate insulating layer, a fifth through hole is etched at a position of the protection layer corresponding to the fourth through hole, and the gate line, the gate line protection layer and the transparent electrode are connected together through the fourth through hole and the fifth through hole. ### Claim 17 (depends on 10) The method according to claim 10, wherein, the array substrate further comprises a chip bonding area, and a step of forming the chip bonding area comprises forming the gate insulating layer, the data line, the protection layer and the transparent electrode on the substrate, wherein, a seventh through hole is etched in the protection layer, and the data line and the transparent electrode are connected together through the seventh through hole. ### Claim 18 (depends on 11) The method according to claim 11, wherein, the array substrate further comprises a common electrode through hole area, and a step of forming the common electrode through hole area comprises forming the gate line, the gate insulating layer, a gate line protection layer, the protection layer and the transparent electrode on the substrate, wherein, a fourth through hole is etched in the gate insulating layer, a fifth through hole is etched at a position of the protection layer corresponding to the fourth through hole, and the gate line, the gate line protection layer and the transparent electrode are connected together through the fourth through hole and the fifth through hole. ### Claim 19 (depends on 11) The method according to claim 11, wherein, the array substrate further comprises a chip bonding area, and a step of forming the chip bonding area comprises forming the gate insulating layer, the data line, the protection layer and the transparent electrode on the substrate, wherein, a seventh through hole is etched in the protection layer, and the data line and the transparent electrode are connected together through the seventh through hole.