# US 2014/0197412 A1 · Circuit board and display device

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- Number: US 2014/0197412 A1
- Document ID: US20140197412A1
- Status: Published application
- Kind: A1
- Application number: 14/215,338
- Filed: 2014-03-17
- Published: 2014-07-17
- Earliest claimed: 2010-04-30
- Assignees: Sharp Kabushiki Kaisha
- Applicants: Sharp Kabushiki Kaisha
- Inventors: Jun NISHIMURA; Hideki KITAGAWA; Atsuhito MURAI; Hajime IMAI; Shinya TANAKA; Mitsunori IMADE; Tetsuo KIKUCHI; Junya SHIMADA; Kazunori MORIMOTO
- Web page: https://patentgrep.com/patent/US20140197412A1

## CPC

- H10D 30/6746: {Amorphous silicon}
- G02F 1/13338: {Input devices, e.g. touch panels}
- G02F 1/13624: {having more than one switching element per pixel}
- G06F 3/0412: {Digitisers structurally integrated in a display}
- H10D 30/6723: {having light shields}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 89/10: Integrated device layouts
- G06F 3/042: by opto-electronic means
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.

## Claims

### Claim 1

A circuit board comprising:
a first transistor element including a first semiconductor layer serving as a channel layer;
a second transistor element including a second semiconductor layer serving as a channel layer; and
a first conductive layer, a second conductive layer and a third conductive layer as electrode formative layers by which the first transistor element and the second transistor element are formed,
the first transistor element and the second transistor element being provided on one surface of a single insulating substrate,
the first conductive layer forming one of a gate electrode and a pair of source and drain electrodes of the first transistor element,
the third conductive layer forming one of a gate electrode and a pair of source and drain electrodes of the second transistor element,
the second conductive layer forming both of (a) the other one of the gate electrode and the pair of source and drain electrodes of the first transistor element and (b) the other one of the gate electrode and the pair of source and drain electrodes of the second transistor element,
one of the first conductive layer and the third conductive layer being formed above the second conductive layer in a thickness direction in which the first conductive layer, the second conductive layer, and the third conductive layer are stacked on the insulating substrate,
the other one of the first conductive layer and the third conductive layer being formed below the second conductive layer in the thickness direction in which the first conductive layer, the second conductive layer, and the third conductive layer are stacked on the insulating substrate.