# US 2014/0197411 A1 · Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0197411 A1
- Document ID: US20140197411A1
- Status: Published application
- Kind: A1
- Application number: 13/743,886
- Filed: 2013-01-17
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: Global Founderies Inc.
- Applicants: Global Founderies Inc.
- Inventors: Vara Govindeswara Reddy VAKADA; Laegu Kang; Michael P. Ganz; Yi Qi; Puneet Khanna; Sri Charan Vemula; Srikanth Samavedam
- Web page: https://patentgrep.com/patent/US20140197411A1

## CPC

- H10D 62/834: further characterised by the dopants
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0278: {forming single crystalline channels on wafers after forming insulating device isolations}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 62/364: {of IGFETs}
- H10D 62/40: Crystalline structures
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/8325: {Silicon carbide}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 32/15: {from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

## Claims

### Claim 1

A method comprising:
providing shallow trench isolation (STI) regions in a silicon wafer;
performing a deep well implantation of a dopant into the silicon wafer between STI regions;
forming a recess in the silicon wafer between the STI regions;
performing a shallow well implantation of the into the silicon wafer in the recess; and
forming carbon-doped silicon (Si:C) on the silicon wafer in the recess.

### Claim 2 (depends on 1)

The method according to claim 1, comprising forming the recess by reactive ion etching (RIE).

### Claim 3 (depends on 1)

The method according to claim 1, comprising forming the recess by an anisotropic wet etch.

### Claim 4 (depends on 1)

The method according to claim 1, comprising annealing the silicon wafer prior to forming the Si:C in the recess.

### Claim 5 (depends on 1)

The method according to claim 1, comprising forming the shallow well implantation at an energy of 5 kiloelectronvolts (keV) to 30 keV and at a dose of 2E13 to 1E14.

### Claim 6 (depends on 1)

The method according to claim 1, comprising forming the Si:C in the recess by epitaxially growing carbon-doped silicon (Si:C) to a thickness of 2 nanometers (nm) to 15 nm.

### Claim 7 (depends on 6)

The method according to claim 6, further comprising epitaxially growing silicon to a thickness of 2 nm to 15 nm on the Si:C.

### Claim 8 (depends on 1)

The method according to claim 1, comprising forming the Si:C in the recess by:
epitaxially growing silicon to a thickness of 3 nm to 15 nm in the recess;
amorphizing the epitaxially grown silicon;
implanting carbon in the amorphized silicon; and
thermally treating the implanted amorphized silicon.

### Claim 9 (depends on 8)

The method according to claim 8, comprising amorphizing the silicon by implanting germanium (Ge).

### Claim 10 (depends on 8)

The method according to claim 8, comprising thermally treating the implanted amorphized silicon by performing a spike rapid thermal anneal (RTA).

### Claim 11 (depends on 8)

The method according to claim 8, further comprising epitaxially growing undoped silicon to a thickness of 0 nm to 15 nm in the recess subsequent to thermally treating the implanted amorphized silicon.

### Claim 12

A device comprising:
a doped silicon substrate;
shallow trench isolation (STI) regions in the silicon substrate; and
carbon-doped silicon (Si:C) formed in a recess formed between STI regions.

### Claim 13 (depends on 12)

The device according to claim 12, wherein the doped silicon substrate is formed by performing a deep well implantation prior to formation of the recess and a shallow well implantation subsequent to formation of the recess.

### Claim 14 (depends on 12)

The device according to claim 12, wherein the Si:C is formed by epitaxial growth to a thickness of 2 nanometers (nm) to 15 nm.

### Claim 15 (depends on 14)

The device according to claim 14, further comprising epitaxially grown silicon on the Si:C in the recess, the epitaxially grown silicon having a thickness of 2 nm to 15 nm.

### Claim 16 (depends on 12)

The device according to claim 12, wherein the Si:C is formed by:
epitaxially growing silicon to a thickness of 3 nm to 15 nm in the recess;
amorphizing the silicon;
implanting carbon in the amorphized silicon; and
thermally treating the amorphized silicon.

### Claim 17 (depends on 16)

The device according to claim 16, further comprising undoped epitaxially grown silicon on the Si:C in the recess, the undoped silicon having a thickness of 0 nm to 15 nm.

### Claim 18 (depends on 16)

The device according to claim 16, wherein the silicon is amorphized by implanting germanium (Ge).

### Claim 19 (depends on 16)

The device according to claim 16, wherein the amorphized silicon is treated by performing a spike rapid thermal anneal (RTA).

### Claim 20

A method comprising:
providing shallow trench isolation (STI) regions in a silicon wafer;
performing a deep well implantation of a p-type dopant into the silicon wafer between the STI regions;
recessing the silicon wafer to a depth of 10 nanometers (nm) to 25 nm between the STI regions;
implanting a p-type dopant into the silicon wafer between the STI regions at an energy of 5 kiloelectronvolts (keV) to 30 keV and at a dose of 2E13 to 1E14;
forming carbon-doped silicon (Si:C) on the doped silicon between the STI regions by:
epitaxially growing Si:C or
epitaxially growing undoped silicon, implanting germanium (Ge) in the undoped silicon, implanting carbon in the Ge doped silicon, and performing a spike rapid thermal anneal (RTA); and
epitaxially growing undoped silicon on the Si:C to a thickness of 0 nm to 15 nm.