# US 2014/0197410 A1 · Semiconductor Structure and Method for Manufacturing the Same

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- Number: US 2014/0197410 A1
- Document ID: US20140197410A1
- Status: Published application
- Kind: A1
- Application number: 13/697,096
- Filed: 2012-05-17
- Published: 2014-07-17
- Earliest claimed: 2011-06-20
- Inventors: Haizhou Yin; Huilong Zhu; Zhijiong Luo
- Web page: https://patentgrep.com/patent/US20140197410A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/40: Crystalline structures
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region. The stressed layer provides a favorable stress to the channel of the semiconductor device, thus facilitating improving the performance of the semiconductor device.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
a) providing an SOI substrate and forming a gate structure (200) on said SOI substrate;
b) etching a SOI layer (100) and a BOX layer (110) of said SOI substrate on both sides of said gate structure (200) to form a trench (140) exposing the BOX layer (110), said trench (140) partially entering into the BOX layer (110);
c) forming a stressed layer (160) by filling up a part of said trench (140); and
d) forming a semiconductor layer (150) to cover the stressed layer (160) in the trench (140).

### Claim 2

A method for manufacturing a semiconductor structure, comprising:
a) providing an SOI substrate and covering a part of said SOI substrate with a mask (400), the part of said SOI substrate covered by the mask being the area that is predetermined for forming a gate line;
b) etching a SOI layer (100) and a BOX layer (110) of said SOI substrate on both sides of said mask (400) to form a trench (140) exposing the BOX layer (110), said trench (140) partially entering into the BOX layer (110);
c) forming a stressed layer (160) by filling up a part of said trench (140);
d) forming a semiconductor layer (150) to cover the stressed layer (160) in the trench (140); and
e) removing the mask to expose the part of said SOI substrate covered by the mask and forming a gate structure (200) thereon.

### Claim 3 (depends on 1)

The method according to claim 1, further comprising forming sidewall spacers (210) on both sides of the gate structure (200) after forming the gate structure (200).

### Claim 4 (depends on 1)

The method according to claim 1, wherein the depth of the trench (140) is within the range of about 50 nm to 150 nm.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the trench (140) exposes a part of an isolation region (120) of the SOI substrate.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the material of the semiconductor layer (150) includes one of polysilicon, amorphous silicon, silicon-germanium and amorphous silicon-germanium, or any combination thereof.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the material of the stressed layer (160) includes silicon nitride.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising: f) forming a source/drain region in the semiconductor layer (150).

### Claim 9

A semiconductor structure comprising an SOI substrate, a gate structure (200), a stressed layer (160) and a semiconductor layer (150), wherein
the SOI substrate includes a SOI layer (100) and a BOX layer (110); the gate structure (200) is formed on the SOI layer (100);
the stressed layer (160) is formed in the SOI substrate on both sides of the gate structure (200) to contact the BOX layer (110) and extend into the BOX layer (110), and the upper surface of the stressed layer (160) is lower than the lower surface of the gate structure (200);
and the stressed layer (160) is covered by the semiconductor layer (150) and the semiconductor layer (150) is in contact with the SOI layer (100).

### Claim 10 (depends on 9)

The semiconductor structure according to claim 9, further comprising sidewall spacers (210) formed on both sides of the gate structure (200).

### Claim 11 (depends on 9)

The semiconductor structure according to claim 9, wherein the thickness of the semiconductor layer (150) is within the range of about 50 nm to 150 nm.

### Claim 12 (depends on 9)

The semiconductor structure according to claim 9, wherein the semiconductor layer (150) and the stressed layer (160) are also in contact with an isolation region (120) of the SOI substrate.

### Claim 13 (depends on 9)

The semiconductor structure according to claim 9, wherein the material of the semiconductor layer (150) includes one of polysilicon, amorphous silicon, silicon-germanium and amorphous silicon-germanium, or any combination thereof.

### Claim 14 (depends on 9)

The semiconductor structure according to claim 9, wherein the material of the stressed layer (160) includes silicon nitride.

### Claim 15 (depends on 9)

The semiconductor structure according to claim 9, wherein a source/drain region is provided in the semiconductor layer (150).

### Claim 16 (depends on 2)

The method according to claim 2, further comprising forming sidewall spacers (210) on both sides of the gate structure (200) after forming the gate structure (200).