# US 2014/0197409 A1 · Multi-chip package and interposer with signal line compression > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197409 A1 - Document ID: US20140197409A1 - Status: Published application - Kind: A1 - Application number: 14/239,110 - Filed: 2012-07-30 - Published: 2014-07-17 - Earliest claimed: 2011-08-17 - Assignees: Rambus Inc. - Inventors: Torsten Partsch - Web page: https://patentgrep.com/patent/US20140197409A1 ## CPC - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 90/00: Package configurations - G01R 31/318505: {Test of Modular systems, e.g. Wafers, MCM's} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10W 70/63: Vias, e.g. via plugs - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A multi-chip package with signal line compression for testing of the multi-chip package. The multi-chip package includes an interposer and two or more integrated circuits attached to the interposer. The interposer includes multiple data signal lines for data communications between the two integrated circuits. The data signal lines are also coupled to one or more test contacts through an interface circuit. The number of test contacts is smaller than the number of signal lines, which allows a large number of signal lines to be tested with a smaller number of test contacts. ## Claims ### Claim 1 An interposer comprising: a substrate; a plurality of data signal lines disposed on the substrate; one or more test contact pads disposed on the substrate configured to receive test data signals, the number N of the contact pads being less than the number M of the data signal lines; and a signal interface circuit configured to route the test data signals from the one or more contact pads to the plurality of data signal lines. ### Claim 2 (depends on 1) The interposer of claim 1, wherein the signal interface circuit comprises one or more switching circuits for routing the test data signals to the plurality of data signal lines. ### Claim 3 (depends on 2) The interposer of claim 2, wherein at least one of the switching circuits is configured to switch the test data signals between two or more of the data signal lines. ### Claim 4 (depends on 2) The interposer of claim 2, wherein at least one of the switching circuits is configured to route the test data signals to two or more of the data signal lines substantially simultaneously. ### Claim 5 (depends on 2) The interposer of claim 2, wherein the one or more switching circuits are implemented in at least one of a thin film transistor layer located on the substrate or in an active layer of the substrate. ### Claim at position 6 6-7. (canceled) ### Claim 8 (depends on 1) The interposer of claim 1, wherein the signal interface circuit comprises an integrated circuit device configured to route the test data signals from the one or more contact pads to the plurality of data signal lines. ### Claim 9 (depends on 8) The interposer of claim 8, wherein the interface circuit further comprises one or more switching circuits coupled to the integrated circuit device and the data signal lines, wherein the plurality of switches are controlled by the integrated circuit device for routing the one or more test data signals from the one or more contact pads to the plurality of data signal lines. ### Claim 10 (depends on 8) The interposer of claim 8, wherein the integrated circuit device is configured to read, from an integrated circuit to be coupled to the data signal lines, test values corresponding to the test data signals applied to the integrated circuit and to check the test values for errors. ### Claim 11 (depends on 10) The interposer of claim 10, further comprising a non-volatile memory disposed on the substrate, the non-volatile rmmiory configured to store information corresponding to an error in the test values detected by the integrated circuit device. ### Claim 12 (depends on 1) The interposer of claim 1, further comprising: a first plurality of integrated circuit (IC) contacts disposed on the substrate and configured to match a pinout of a first IC; and a second plurality of IC contacts disposed on the substrate and configured to match a pinout of a second IC; wherein the plurality of data signal lines connect the first plurality of IC contacts with the second plurality of IC contacts. ### Claim at position 12 13-14. (canceled) ### Claim 15 A multi-chip package comprising: a memory device; a memory controller device; and an interposer including: a plurality of data signal lines connecting the memory device with the memory controller device; one or more test contact pads configured to receive test data signals, the number N of contact pads being less than the number M of data signal lines; and a signal interface circuit configured to route the test data signals from the contact pads to the data signal lines. ### Claim 16 (depends on 15) The package of claim 15, wherein the signal interface circuit comprises one or more switching circuits for routing the One or more test data signals to the plurality of data signal lines. ### Claim 17 (depends on 16) The package of claim 16, wherein at least one of the switching circuits is configured to switch the test data signals between two or more of the data signal lines. ### Claim 18 (depends on 16) The package of claim 16, wherein at least one of the switching circuits is configured to route the test data signals to two or more of the data signal lines substantially simultaneously. ### Claim 19 (depends on 16) The package of claim 16, wherein the one or more switching circuits are implemented in at least one of a thin film transistor layer located on a substrate of the interposer or in an active layer of the substrate of the interposer. ### Claim at position 18 20-21. (canceled) ### Claim 22 (depends on 15) The package of claim 15, wherein the signal interface circuit comprises an integrated circuit device configured to route the test data signals from the one or more contact pads to the plurality of data signal lines. ### Claim 23 (depends on 22) The package of claim 22, wherein the signal interface circuit further comprises one or more switching circuits coupled to the integrated circuit device and the signal lines, wherein the plurality of switches are controlled by the integrated circuit device for routing the one or more test data signals from the one or more contact pads to the plurality of data signal lines. ### Claim 24 (depends on 22) The package of claim 22, wherein the memory device stores test values corresponding to the test data signals, and the signal interface circuit further comprises an error detection circuit configured to read the stored test values from the memory device and to check the test values for errors. ### Claim 25 (depends on 24) The package of claim 24, where the interposer further comprises a non-volatile memory, the non-volatile memory configured to store information corresponding to an error in the test values detected by the integrated circuit device. ### Claim at position 23 26-31. (canceled) ### Claim 32 A multi-chip package comprising: a memory device; a memory controller device; and an interposer including: a plurality of data signal lines connecting the memory device with the memory controller device; one or more test contact pads configured to receive test data signals, the number N of contact pads being less than the number M of data signal lines; and one or more IC contacts that are connected to the one or more test contact pads, the IC contacts configured to match a pinout of an integrated circuit device that routes the test data signals from the one or more contact pads to the plurality of data signal lines.