# US 2014/0197408 A1 · Thin-film transistor

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- Number: US 2014/0197408 A1
- Document ID: US20140197408A1
- Status: Published application
- Kind: A1
- Application number: 14/238,019
- Filed: 2012-08-08
- Published: 2014-07-17
- Earliest claimed: 2011-08-11
- Assignees: Idemitsu Kosan Co., Ltd.
- Inventors: Yuki Tsuruma; Kazuaki Ebata; Shigekazu Tomai; Shigeo Matsuzaki
- Web page: https://patentgrep.com/patent/US20140197408A1

## CPC

- H10D 30/6756: {Amorphous oxide semiconductors}
- C23C 14/0057: {using reactive gases other than O2, H2O, N2, NH3 or CH4}
- C23C 14/086: {of zinc, germanium, cadmium, indium, tin, thallium or bismuth}
- C23C 14/34: Sputtering
- C23C 14/3414: {Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/3446: {Transition metal elements; Rare earth elements}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A thin film transistor (1) includes a source electrode (50), a drain electrode (60), a gate electrode (20), a gate insulating film (30), and a channel layer (40) that is formed of an oxide semiconductor, the channel layer (40) having an average carrier concentration of 1×1016/cm3 to 5×1019/cm3, and including a high carrier concentration region (42) that is situated on the side of the gate insulating film (30) and has a carrier concentration higher than the average carrier concentration, and the channel layer (40) having a substantially homogenous composition.

## Claims

### Claim 1

A thin film transistor comprising a source electrode, a drain electrode, a gate electrode, a gate insulating film, and a channel layer that is formed of an oxide semiconductor,
the channel layer having an average carrier concentration of 1×1016/cm3 to 5×1019/cm3, and comprising a high carrier concentration region that is situated on a side of the gate insulating film and has a carrier concentration higher than the average carrier concentration, and
the channel layer having a substantially homogeneous composition.

### Claim 2 (depends on 1)

The thin film transistor according to claim 1,
wherein the channel layer has a thickness of 10 nm or more, and the high carrier concentration region has an average carrier concentration of 1×1018/cm3 to 5×1021/cm3.

### Claim 3 (depends on 1)

The thin film transistor according to claim 1,
wherein the high carrier concentration region is a region of the channel layer up to a depth of 5 nm from an interface with the gate insulating film.

### Claim 4 (depends on 1)

The thin film transistor according to claim 1,
wherein the oxide semiconductor has a crystalline structure.

### Claim 5 (depends on 1)

The thin film transistor according to claim 1,
wherein the oxide semiconductor is indium oxide, Ga-doped indium oxide, Al-doped indium oxide, Ga—Al-doped indium oxide, Zn-doped indium oxide, or Sn-doped indium oxide.

### Claim 6 (depends on 5)

The thin film transistor according to claim 5,
wherein the Ga-doped indium oxide has an atomic ratio “Ga/(Ga+In)” of 0.007 to 0.207.

### Claim 7 (depends on 5)

The thin film transistor according to claim 5, wherein the Al-doped indium oxide has an atomic ratio “Al/(Al+In)” of 0.003 to 0.125.

### Claim 8 (depends on 1)

The thin film transistor according to claim 1, the thin film transistor having a bottom-gate structure.

### Claim 9 (depends on 8)

The thin film transistor according to claim 8, further comprising a protective layer that is formed on the channel layer.

### Claim 10 (depends on 9)

The thin film transistor according to claim 9,
wherein the protective layer is an insulating film having oxygen permeability.

### Claim 11 (depends on 1)

The thin film transistor according to claim 1, the thin film transistor having a top-gate structure.