# US 2014/0197377 A1 · Cmos nanowire structure

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- Number: US 2014/0197377 A1
- Document ID: US20140197377A1
- Status: Published application
- Kind: A1
- Application number: 13/996,503
- Filed: 2011-12-23
- Published: 2014-07-17
- Earliest claimed: 2011-12-23
- Assignees: Intel Corporation
- Inventors: Seiyon Kim; Kelin J. Kuhn; Tahir Ghani; Anand S. Murthy; Annalisa Cappellani; Stephen M. Cea; Rafael Rios; Glenn A. Glass
- Web page: https://patentgrep.com/patent/US20140197377A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first semiconductor device comprising:
a first nanowire disposed above a substrate, the first nanowire having a mid-point a first distance above the substrate and comprising a discrete channel region and source and drain regions on either side of the discrete channel region; and
a first gate electrode stack completely surrounding the discrete channel region of the first nanowire; and
a second semiconductor device comprising:
a second nanowire disposed above the substrate, the second nanowire having a mid-point a second distance above the substrate and comprising a discrete channel region and source and drain regions on either side of the discrete channel region, the first distance different from the second distance; and
a second gate electrode stack completely surrounding the discrete channel region of the second nanowire.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first nanowire consists essentially of a material selected from the group consisting of silicon, strained silicon, silicon germanium (SixGey, where 0<x<100, and 0<y<100), silicon carbide, carbon doped silicon germanium and a group III-V compound, and the second nanowire consists essentially of a different material selected from the group consisting of silicon, strained silicon, silicon germanium (SixGey, where 0<x<100, and 0<y<100), carbon doped silicon germanium and a group III-V compound.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the first semiconductor device is an NMOS device, and the second semiconductor device is a PMOS device.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the first and second nanowires are disposed above a bulk crystalline substrate having an intervening dielectric layer disposed thereon.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the first and second nanowires are disposed above a bulk crystalline substrate having no intervening dielectric layer disposed thereon.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the source and drain regions of each of the first and second nanowires are discrete, the first semiconductor device further comprising a first pair of contacts completely surrounding the discrete source and drain regions of the first nanowire, and the second semiconductor device further comprising a second pair of contacts completely surrounding the discrete source and drain regions of the second nanowire.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, further comprising:
a first pair of spacers disposed between the first gate electrode stack and the first pair of contacts; and
a second pair of spacers disposed between the second gate electrode stack and the second pair of contacts.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein a portion of each of the first and second nanowires is non-discrete.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the first semiconductor device further comprises one or more additional nanowires vertically stacked with the first nanowire, the first nanowire being the bottommost nanowire of the first semiconductor device, and the second semiconductor device further comprises one or more additional nanowires vertically stacked with the second nanowire, the second nanowire being the bottommost nanowire of the second semiconductor device.

### Claim 10

A semiconductor structure, comprising:
a first semiconductor device comprising:
a first nanowire disposed above a substrate, the first nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region, the discrete channel region comprising a semiconductor backbone material; and
a first gate electrode stack completely surrounding the discrete channel region of the first nanowire; and
a second semiconductor device comprising:
a second nanowire disposed above the substrate, the second nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region, the discrete channel region comprising the semiconductor backbone material as well as a surrounding cladding material layer not included in the channel region of the first semiconductor device; and
a second gate electrode stack completely surrounding the discrete channel region of the second nanowire.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the first nanowire further comprises a surrounding cladding material layer different from the cladding material layer of the second nanowire.

### Claim 12 (depends on 10)

The semiconductor structure of claim 10, wherein the first nanowire does not comprises a surrounding cladding material layer.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10, wherein the semiconductor backbone material of the first and second nanowire is formed from the same layer.

### Claim 14 (depends on 10)

The semiconductor structure of claim 10, wherein the semiconductor backbone material of the second nanowire has a smaller diameter than the semiconductor backbone material of the first nanowire.

### Claim 15 (depends on 10)

The semiconductor structure of claim 10, wherein the semiconductor backbone material is selected from the group consisting of silicon, strained silicon, silicon germanium (SixGey, where 0<x<100, and 0<y<100), silicon carbide, carbon doped silicon germanium and a group III-V compound, and the cladding material layer consists essentially of a different material selected from the group consisting of silicon, strained silicon, silicon germanium (SixGey, where 0<x<100, and 0<y<100), silicon carbide, carbon doped silicon germanium and a group III-V compound.

### Claim 16 (depends on 10)

The semiconductor structure of claim 10, wherein the first and second nanowires are disposed above a bulk crystalline substrate having an intervening dielectric layer disposed thereon.

### Claim 17 (depends on 10)

The semiconductor structure of claim 10, wherein the first and second nanowires are disposed above a bulk crystalline substrate having no intervening dielectric layer disposed thereon.

### Claim 18 (depends on 10)

The semiconductor structure of claim 10, wherein the source and drain regions of each of the first and second nanowires are discrete, the first semiconductor device further comprising a first pair of contacts completely surrounding the discrete source and drain regions of the first nanowire, and the second semiconductor device further comprising a second pair of contacts completely surrounding the discrete source and drain regions of the second nanowire.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, further comprising:
a first pair of spacers disposed between the first gate electrode stack and the first pair of contacts; and
a second pair of spacers disposed between the second gate electrode stack and the second pair of contacts.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein a portion of each of the first and second nanowires is non-discrete.

### Claim 21 (depends on 10)

The semiconductor structure of claim 10, wherein the first semiconductor device further comprises one or more additional nanowires vertically stacked with the first nanowire, and the second semiconductor device further comprises one or more additional nanowires vertically stacked with the second nanowire.

### Claim 22

A method of fabricating a CMOS nanowire semiconductor structure, the method comprising:
forming a first active layer above a substrate, the first active layer having a first lattice constant;
forming a second active layer on the first active layer, the second active layer having a second lattice constant greater than the first lattice constant;
forming, from the first active layer, a first nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region;
forming, from the second active layer, a second nanowire comprising a discrete channel region and source and drain regions on either side of the discrete channel region;
forming a first gate electrode stack completely surrounding the discrete channel region of the first nanowire; and
forming a second gate electrode stack completely surrounding the discrete channel region of the second nanowire.

### Claim 23 (depends on 22)

The method of claim 22, wherein forming the first nanowire from the first active layer comprises selectively removing a portion of the second active layer, and forming the second nanowire from the second active layer comprises selectively removing a portion of the first active layer.

### Claim 24 (depends on 22)

The method of claim 22, wherein the first active layer consists essentially of silicon, and the second active layer consists essentially of silicon germanium (SixGey, where 0<x<100, and 0<y<100).

### Claim 25 (depends on 24)

The method of claim 24, wherein the first gate electrode stack is an NMOS gate electrode stack, and wherein the second gate electrode stack is a PMOS gate electrode stack.

### Claim 26 (depends on 22)

The method of claim 22, wherein the first active layer is formed above a bulk crystalline substrate having an intervening dielectric layer disposed thereon, the first active layer formed on the intervening dielectric layer.

### Claim 27 (depends on 22)

The method of claim 22, wherein the first active layer is formed from a bulk crystalline substrate.