# US 2014/0197376 A1 · Semiconductor Device

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- Number: US 2014/0197376 A1
- Document ID: US20140197376A1
- Status: Published application
- Kind: A1
- Application number: 13/812,504
- Filed: 2012-10-12
- Published: 2014-07-17
- Earliest claimed: 2012-08-16
- Assignees: Institute of Microelectronics Chinese Academy of Sciences (IMECAS)
- Inventors: Xiaolong Ma; Huaxiang Yin; Sen Xu; Huilong Zhu
- Web page: https://patentgrep.com/patent/US20140197376A1

## CPC

- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

## Claims

### Claim 1

A semiconductor device comprising a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the concentration of Ge in the buffer layer and/or the barrier layer and/or the inversely doped isolation layer is greater than 50%.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the concentration of Sn in the buffer layer and/or the barrier layer and/or the inversely doped isolation layer is less than 25%.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the thickness of the buffer layer is 100 nm-2 μm.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the concentration of Sn in the channel layer is greater than 1% and less than 25%.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the thickness of the channel layer is 5 nm-200 nm.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein a cap layer formed of the SiGe alloy is disposed between the channel layer and the gate stack structure.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the source and drain regions are formed of a SiGeSn alloy.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the source and drain regions have a first conductivity type, and the inversely doped isolation layer, the barrier layer and the channel region have a second conductivity type opposite to the first conductivity type.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the forbidden-band width of the material of the barrier layer is greater than the band gap width of the material of the channel layer.