# US 2014/0197371 A1 · Overlap capacitance nanowire

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- Number: US 2014/0197371 A1
- Document ID: US20140197371A1
- Status: Published application
- Kind: A1
- Application number: 13/970,931
- Filed: 2013-08-20
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Effendi Leobandung
- Web page: https://patentgrep.com/patent/US20140197371A1

## CPC

- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectic regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.

## Claims

### Claim 1

A semiconductor device, comprising:
one or more structures formed on a substrate;
a top gate formed above the one or more structures and between first spacers;
a bottom gate formed below the one or more structures and between second spacers such that the one or more structures are directly on the bottom gate, the second spacers formed on a portion of the first spacers, wherein the second spacers include a vertical portion having an inner sidewall that is in contact with the bottom gate that is aligned with a sidewall of the first spacers that are in contact with the top gate, and the second spacers having a horizontal portion present between the substrate and portions of the one or more structures that are adjacent to a portion of the substrate that the top gate is overlying; and
source/drain regions having interlayer dielectric regions formed thereon.

### Claim 2 (depends on 1)

The semiconductor device as recited in claim 1, wherein edges of the top gate and the bottom gate are aligned.

### Claim 3 (depends on 1)

The semiconductor device as recited in claim 1, wherein the bottom gate is formed above the substrate.

### Claim 4 (depends on 1)

The semiconductor device as recited in claim 1, wherein the bottom gate is laterally disposed between undercut etched portions.

### Claim 5 (depends on 4)

The semiconductor device as recited in claim 4, wherein the undercut etched portions include dielectric material.

### Claim 6 (depends on 1)

The semiconductor device as recited in claim 1, wherein the top gate includes a top metal gate and the bottom gate includes a bottom metal gate.

### Claim 7 (depends on 1)

The semiconductor device as recited in claim 1, wherein the one or more structures include one or more fins.

### Claim 8 (depends on 5)

The semiconductor device as recited in claim 5, wherein the one or more fins include one or more fins for a nanowire.