# US 2014/0197370 A1 · Overlap capacitance nanowire

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- Number: US 2014/0197370 A1
- Document ID: US20140197370A1
- Status: Published application
- Kind: A1
- Application number: 13/739,182
- Filed: 2013-01-11
- Published: 2014-07-17
- Earliest claimed: 2013-01-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: EFFENDI LEOBANDUNG
- Web page: https://patentgrep.com/patent/US20140197370A1

## CPC

- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectric regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.

## Claims

### Claim 1

A method for fabricating a nanowire, comprising:
etching exposed portions of the a substrate to provide an unetched raised portion, the substrate having a first set of structures formed thereon and a dummy structure formed over at least a portions of the substrate and the first set of structures;
forming first spacers about a periphery of the dummy structure and the unetched raised portion;
etching the substrate to form controlled undercut etched portions around a portion of the substrate below the dummy structure;
forming second spacers in the controlled undercut etched portions;
removing the dummy structure;
etching the substrate to release the first set of structures; and
forming gate structures including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures such that the second spacers are employed to align edges of the bottom gate to the top gate.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein forming gate structures includes forming metal gate structures.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein forming gate structures includes forming the top gate and the bottom gate such that edges of the top gate and bottom gate are aligned.

### Claim 4 (depends on 1)

The method as recited in claim 1, wherein forming gate structures includes forming the bottom gate between the second spacers.

### Claim 5 (depends on 1)

The method as recited in claim 1, wherein etching the substrate to release the first set of structures includes etching the portion of the substrate below the dummy structure to release the first set of structures.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein etching exposed portions of the substrate includes etching exposed portions of the substrate that are not masked by the dummy structure or the first set of structures.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein etching the substrate to form controllable undercut etched portions includes etching a portion of the substrate below the first spacers.

### Claim 8 (depends on 1)

The method as recited in claim 1, wherein the first set of structures includes one or more fin structures.

### Claim 9 (depends on 1)

The method as recited in claim 1, wherein the dummy structure includes polysilicon.

### Claim 10

A method for fabricating a nanowire, comprising:
patterning fin structures on a substrate;
forming a dummy structure over portions of the substrate and the fin structures;
etching exposed portions of the substrate to provide an unetched raised portion;
forming first sidewall spacers about a periphery of the dummy structure and the unetched raised portion;
etching the substrate to form controlled undercut etched portions around a portion of the substrate below the dummy structure;
forming second spacers in the controlled undercut etched portions;
forming source/drain regions with interlayer dielectric regions formed thereon;
removing the dummy structure;
etching the substrate to release the fin structures; and
forming metal gate structures including a top gate formed above the fin structures and a bottom gate formed below the fin structures to provide a nanowire such that the second spacers are employed to align edges of the bottom gate to the top gate.

### Claim 11 (depends on 10)

The method as recited in claim 10, wherein forming gate structures includes forming a bottom gate between the second spacers.

### Claim 12 (depends on 10)

The method as recited in claim 10, wherein etching the substrate to release the fin structures includes etching the portion of the substrate below the dummy structure to release the fin structures.

### Claim 13 (depends on 10)

The method as recited in claim 10, wherein etching exposed portions of the substrate includes etching exposed portions of the substrate that are not masked by the dummy structure or the fin structures.

### Claim 14 (depends on 10)

The method as recited in claim 10, wherein the dummy structure includes polysilicon.

### Claim at position 15

15-22. (canceled)

### Claim 23 (depends on 1)

The method as recited in claim 1, further comprising forming source/drain regions with interlayer dielectric regions formed thereon.