# US 2014/0197368 A1 · Nonvolatile memory element, nonvolatile memory device, nonvolatile memory element manufacturing method, and nonvolatile memory device manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197368 A1 - Document ID: US20140197368A1 - Status: Published application - Kind: A1 - Application number: 14/343,441 - Filed: 2012-09-10 - Published: 2014-07-17 - Earliest claimed: 2011-09-16 - Assignees: Panasonic Corporation - Inventors: Shinichi Yoneda; Takumi Mikawa; Satoru Ito; Yukio Hayakawa; Atsushi Himeno - Web page: https://patentgrep.com/patent/US20140197368A1 ## CPC - H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices} - H10N 70/021: {Formation of switching materials, e.g. deposition of layers} - H10N 70/026: {by physical vapor deposition, e.g. sputtering} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/828: {Current flow limiting means within the switching material region, e.g. constrictions} - H10N 70/883: {Oxides or nitrides} - H10N 70/8833: {Binary metal oxides, e.g. TaOx} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide. ## Claims ### Claim at position 1 1-15. (canceled) ### Claim 16 A nonvolatile memory element comprising: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode, the variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the first electrode and the second electrode; a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer which is connected to neither the first electrode nor the second electrode; and an interlayer insulating layer formed to cover the variable resistance layer and the side wall protecting layer, wherein the first variable resistance layer comprises a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than an oxygen deficiency of the first metal oxide, and the second variable resistance layer comprises a second metal oxide having an oxygen deficiency lower than the oxygen deficiency of the first metal oxide, and the side wall protecting layer covers at least a side surface of the third metal oxide to prevent oxygen in the interlayer insulating layer from diffusing into the third metal oxide. ### Claim 17 A nonvolatile memory element comprising: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode, the variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the first electrode and the second electrode; a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer which is connected to neither the first electrode nor the second electrode; and an interlayer insulating layer formed to cover the variable resistance layer and the side wall protecting layer, wherein the first variable resistance layer comprises a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen content atomic percentage higher than an oxygen content atomic percentage of the first metal oxide, and the second variable resistance layer comprises a second metal oxide having an oxygen content atomic percentage higher than the oxygen content atomic percentage of the first metal oxide, and the side wall protecting layer covers at least a side surface of the third metal oxide to prevent oxygen in the interlayer insulating layer from diffusing into the third metal oxide. ### Claim 18 (depends on 16) The nonvolatile memory element according to claim 16, wherein the side wall protecting layer further covers a side surface of the first electrode and a side surface and a top surface of the second electrode. ### Claim 19 (depends on 16) The nonvolatile memory element according to claim 16, wherein the side wall protecting layer comprises one of a metal oxide, a metal nitride, and a metal acid nitride that have insulation properties and oxygen barrier properties. ### Claim 20 (depends on 16) The nonvolatile memory element according to claim 16, wherein the side wall protecting layer comprises one of a silicon nitride, an aluminum oxide, and a titanium oxide. ### Claim 21 (depends on 16) The nonvolatile memory element according to claim 16, wherein the first metal oxide has a stack structure of a plurality of layers comprising metal oxides having different oxygen deficiencies. ### Claim 22 (depends on 16) The nonvolatile memory element according to claim 16, wherein each of the first metal oxide, the second metal oxide, and the third metal oxide is one of a tantalum oxide, a hafnium oxide, and a zirconium oxide. ### Claim 23 (depends on 16) The nonvolatile memory element according to claim 16, wherein the second variable resistance layer is provided with a localized region having an oxygen deficiency that reversibly changes in response to an application of an electric pulse. ### Claim 24 A nonvolatile memory element manufacturing method comprising: forming a laminated film including, as layers, a first electrode material, a first metal oxide, a second metal oxide, and a second electrode material in this order, the second metal oxide having an oxygen deficiency lower than an oxygen deficiency of the first metal oxide; patterning the laminated film to leave a portion of the laminated film to be a nonvolatile memory element, and remove an other portion of the laminated film; forming a third metal oxide around the first metal oxide by oxidizing a side surface of the first metal oxide exposed by the patterning, the third metal oxide having an oxygen deficiency lower than the oxygen deficiency of the first metal oxide; covering at least a side surface of the third metal oxide with a side wall protecting layer having oxygen barrier properties; and forming an interlayer insulating layer to cover the variable resistance layer and the side wall protecting layer, wherein the side wall protecting layer covers at least the side surface of the third metal oxide to prevent oxygen in the interlayer insulating layer from diffusing into the third metal oxide. ### Claim 25 (depends on 24) The nonvolatile memory element manufacturing method according to claim 24, further comprising forming a localized region in the second metal oxide by applying a first electrical pulse between the first electrode material and the second electrode material, the localized region having an oxygen deficiency that reversibly changes in response to an application of a second electrical pulse between the first electrode material and the second electrode material, and the second electrical pulse having an amplitude less than an amplitude of the first electrical pulse. ### Claim 26 (depends on 16) A nonvolatile memory device comprising a plurality of memory cell arrays which are stacked with an interlayer insulating film therebetween and each of which includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction different from the first direction; a plurality of the nonvolatile memory elements according to claim 16 which are disposed at respective three-dimensional cross points of the first lines and the second lines and each of which is connected to one of the first lines and one of the second lines; a plurality of first contact plugs each of which connects one of the first electrodes of the nonvolatile memory elements and one of the first lines; and a plurality of second contact plugs each of which connects one of the second electrodes of the nonvolatile memory elements and one of the second lines. ### Claim 27 (depends on 26) The nonvolatile memory device according to claim 26, wherein the interlayer insulating film comprises one of TEOS, FSG, and Si3N4, and the first contact plugs and the second contact plugs comprise tungsten. ### Claim 28 A nonvolatile memory device manufacturing method comprising: forming a plurality of first lines extending in a first direction; forming a first interlayer insulating layer covering the first lines; forming, in the first interlayer insulating layer, a plurality of first contact plugs that are connected to one of the first lines; forming, above the first contact plugs, a laminated film that is connected to the first contact plugs and includes, as layers, a first electrode material, a first metal oxide, a second metal oxide, and a second electrode material in this order, the second metal oxide having an oxygen deficiency lower than an oxygen deficiency of the first metal oxide; patterning the laminated film to leave a plurality of portions of the laminated film to be connected to the first contact plugs, and remove an other portion of the laminated film; forming a third metal oxide around the first metal oxide by oxidizing a side surface of the first metal oxide exposed by the patterning, the third metal oxide having an oxygen deficiency lower than the oxygen deficiency of the first metal oxide; covering at least a side surface of the third metal oxide with a side wall protecting layer having oxygen barrier properties; forming a second interlayer insulating layer covering the patterned laminated film and the side wall protecting layer; forming, in the second interlayer insulating layer, a plurality of second contact plugs that are connected to the patterned laminated film; and forming, above the second contact plugs, a plurality of second lines extending in a second direction different from the first direction, wherein the side wall protecting layer covers at least the side surface of the third metal oxide to prevent oxygen in the interlayer insulating layer from diffusing into the third metal oxide. ### Claim 29 (depends on 28) The nonvolatile memory device manufacturing method according to claim 28, further comprising forming a localized region in the second metal oxide by applying a first electrical pulse between one of the first lines and one of the second lines, the localized region having an oxygen deficiency that reversibly changes in response to an application of a second electrical pulse between the first line and the second line, and the second electrical pulse having an amplitude less than an amplitude of the first electrical pulse. ### Claim 30 (depends on 17) A nonvolatile memory device comprising a plurality of memory cell arrays which are stacked with an interlayer insulating film therebetween and each of which includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction different from the first direction; a plurality of the nonvolatile memory elements according to claim 17 which are disposed at respective three-dimensional cross points of the first lines and the second lines and each of which is connected to one of the first lines and one of the second lines; a plurality of first contact plugs each of which connects one of the first electrodes of the nonvolatile memory elements and one of the first lines; and a plurality of second contact plugs each of which connects one of the second electrodes of the nonvolatile memory elements and one of the second lines.