# US 2014/0197303 A1 · Focal plane array processing method and apparatus

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- Number: US 2014/0197303 A1
- Document ID: US20140197303A1
- Status: Published application
- Kind: A1
- Application number: 14/221,429
- Filed: 2014-03-21
- Published: 2014-07-17
- Earliest claimed: 2006-10-27
- Assignees: Massachusetts Institute of Technology
- Inventors: MICHAEL KELLY; BRIAN TYRRELL; CURTIS COLONERO; ROBERT BERGER; KENNETH SCHULTZ; JAMES WEY; DANIEL MOONEY; LAWRENCE CANDELL
- Web page: https://patentgrep.com/patent/US20140197303A1

## CPC

- H04N 5/913: for scrambling {; for copy protection}
- G06F 21/602: {Providing cryptographic facilities or services}
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- G11B 20/00086: {Circuits for prevention of unauthorised reproduction or copying, e.g. piracy (indicating unauthorised use of record carriers in general G11B23/28; scrambling for television signal recording H04N5/913; network architectures or network protocols for network security H04L63/00; cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00)}
- G11B 20/0021: {involving encryption or decryption of contents recorded on or reproduced from a record carrier}
- H04L 9/0631: {Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms}
- H04L 9/0637: {Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]}
- H04L 9/12: Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
- H04N 5/772: {the recording apparatus and the television camera being placed in the same enclosure}
- H04N 21/4223: Cameras (H04N23/00 takes precedence)
- H04N 21/4408: involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
- H04N 23/20: for generating image signals from infrared radiation only
- H04N 25/57: Control of the dynamic range
- H04N 25/707: Pixels for event detection
- H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N 25/772: comprising A/D, V/T, V/F, I/T or I/F converters
- H04L 2209/12: Details relating to cryptographic hardware or logic circuitry
- H04L 2209/805: Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
- H04N 2005/91364: {the video signal being scrambled}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.

## Claims

### Claim 1

An apparatus comprising:
a two-dimensional array of photodetectors; and
a two-dimensional array of analog-to-digital converters (ADCs), wherein at least one ADC in the two-dimensional array of ADCs comprises:
a capacitor operably coupled to a photodetector in the two-dimensional array of photodetectors to integrate current from the photo detector;
a comparator operably coupled to the capacitor to generate a latch signal when a voltage across the capacitor reaches a reference voltage; and
a voltage source operably coupled to the capacitor to charge the capacitor to a reset voltage between ground and the reference voltage after the comparator generates the latch signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein a frequency of the latch signal is independent of a capacitance of the capacitor and of the reference voltage.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a switch to disconnect the voltage source from the capacitor while the capacitor integrates the current from the photodetector.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising a transistor that operably couples the photodetector to the capacitor.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the at least one ADC further comprises a counter to latch a count value based on the latch signal.

### Claim 6 (depends on 5)

The apparatus of claim 5, further comprising a clock to generate a clock signal that determines a count rate of the counter.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the counter is a modulo M counter.

### Claim 8

An apparatus comprising:
a two-dimensional array of photodetectors; and
a two-dimensional array of analog-to-digital converters (ADCs) operably coupled to the two-dimensional array of photodetectors, wherein at least one ADC in the two-dimensional array of ADCs comprises:
a modulo M counter to store a count value representing a current generated by a corresponding photodetector in the two-dimensional array of photodetectors.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein M is the product of two prime numbers.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the modulo M counter is a bidirectional counter.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the at least one ADC further comprises a capacitor to integrate the current generated by the corresponding photodetector.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the at least one ADC further comprises at least one of a voltage-to-frequency converter and a comparator to convert a voltage across the capacitor to a signal that increments or decrements the count value stored in the modulo M counter.