# US 2014/0196941 A1 · Optimized via cutouts with ground references

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- Number: US 2014/0196941 A1
- Document ID: US20140196941A1
- Status: Published application
- Kind: A1
- Application number: 13/742,168
- Filed: 2013-01-15
- Published: 2014-07-17
- Earliest claimed: 2013-01-15
- Assignees: Fujitsu Limited
- Applicants: Fujitsu Limited
- Inventors: Yasuo Hidaka; Pradip Thachile
- Web page: https://patentgrep.com/patent/US20140196941A1

## CPC

- H05K 1/116: {Lands, clearance holes or other lay-out details concerning the surrounding of a via}
- G06F 30/00: Computer-aided design [CAD]
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines}
- H05K 1/0251: {related to vias or transitions between vias and transmission lines}
- G06F 2115/12: Printed circuit boards [PCB] or multi-chip modules [MCM]
- H05K 1/0225: {Single or multiple openings in a shielding, ground or power plane (H05K1/0227 takes precedence)}
- H05K 1/0253: {Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence)}
- H05K 2201/09718: Clearance holes
- H05K 2201/09727: Varying width along a single conductor; Conductors or pads having different widths
- Y10T 29/49165: by forming conductive walled aperture in base
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

## Claims

### Claim 1

A method of optimizing via cutouts, comprising:
selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry of the via cutout selected to provide an extension region extending in the direction of the first differential trace;
selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region; and
selecting a radial dimension of a first via cutout and a second via cutout on a second ground reference layer adjacent to and between the first differential trace and a second differential trace, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

### Claim 2 (depends on 1)

The method of claim 1, wherein the spacing of the first differential trace in the extension region is greater than the spacing of the first differential trace outside the extension region.

### Claim 3 (depends on 1)

The method of claim 1, wherein a width of the first differential trace in the extension region is narrower than a width of the first differential trace outside the extension region.

### Claim 4 (depends on 1)

The method of claim 1, wherein the extension region is rectangular.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
if there is a third ground reference layer adjacent to and between the second differential trace and a third differential trace, selecting a radial dimension of a first via cutout and a second via cutout on the third ground reference layer;
wherein the radial dimension of the first via cutout and the second via cutout is selected such that the third ground reference layer remains intact in the area adjacent the third differential trace.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
if there is a third ground reference layer adjacent to the second differential trace, but not between the second differential trace and a third differential trace:
selecting a geometry of a via cutout on the third ground reference layer, the geometry of the via cutout selected to provide an extension region extending in the direction of the second differential trace; and
selecting a geometry of the second differential trace, wherein a spacing of the second differential trace in the extension region is different from a spacing of the second differential trace outside the extension region.

### Claim 7 (depends on 6)

The method of claim 6, wherein the spacing of the second differential trace in the extension region is greater than the spacing of the second differential trace outside the extension region.

### Claim 8 (depends on 6)

The method of claim 6, wherein a width of the second differential trace in the extension region is narrower than a width of the second differential trace outside the extension region.

### Claim 9 (depends on 6)

The method of claim 6, wherein the extension region is rectangular.

### Claim 10

A printed circuit board comprising:
a first ground reference layer;
a second ground reference layer;
a via cutout on the first ground reference layer, the geometry of the via cutout selected to provide an extension region extending in the direction of a differential trace,
a first differential trace, the first differential trace adjacent a first ground reference layer and a second ground reference layer, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region;
a second differential trace; the second differential trace adjacent the second ground reference layer; and
a first via cutout and a second via cutout on the second ground reference layer, a radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

### Claim 11 (depends on 10)

The printed circuit board of claim 10, wherein the spacing of the first differential trace in the extension region is greater than the spacing of the first differential trace outside the extension region.

### Claim 12 (depends on 10)

The printed circuit board of claim 10, wherein a width of the first differential trace in the extension region is narrower than a width of the first differential trace outside the extension region.

### Claim 13 (depends on 10)

The printed circuit board of claim 10, wherein the extension region is rectangular.

### Claim 14 (depends on 10)

The printed circuit board of claim 10, further comprising:
a third differential trace;
a third ground reference layer adjacent to and between the second differential trace and the third differential trace,
a first via cutout and a second via cutout on the third ground reference layer, a radial dimension of the first via cutout and the second via cutout selected such that the third ground reference layer remains intact in the area adjacent the third differential trace.

### Claim 15 (depends on 10)

The printed circuit board of claim 10, further comprising:
a third ground reference layer adjacent to the second differential trace, but not between the second differential trace and a third differential trace:
a via cutout on the third ground reference layer, the geometry of the via cutout selected to provide an extension region extending in the direction of the second differential trace; and
wherein a spacing of the second differential trace in the extension region is different from a spacing of the second differential trace outside the extension region.

### Claim 16 (depends on 15)

The printed circuit board of claim 15, wherein the spacing of the second differential trace in the extension region is greater than the spacing of the second differential trace outside the extension region.

### Claim 17 (depends on 15)

The printed circuit board of claim 15, wherein a width of the second differential trace in the extension region is narrower than a width of the second differential trace outside the extension region.

### Claim 18 (depends on 15)

The printed circuit board of claim 15, wherein the extension region is rectangular.