# US 2014/0196934 A1 · Wiring substrate and electronic device

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- Number: US 2014/0196934 A1
- Document ID: US20140196934A1
- Status: Published application
- Kind: A1
- Application number: 14/233,984
- Filed: 2012-06-29
- Published: 2014-07-17
- Earliest claimed: 2011-07-22
- Assignees: KYOCERA Corporation
- Inventors: Hiroshi Kawagoe; Kazuhiko Yagi
- Web page: https://patentgrep.com/patent/US20140196934A1

## CPC

- H05K 1/0209: {External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H05K 1/0204: {using means for thermal conduction connection in the thickness direction of the substrate (H05K1/0207 takes precedence)}
- H05K 3/246: {Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating}
- H05K 2201/10416: Metallic blocks or heatsinks completely inserted in a PCB
- H10H 20/8581: {characterised by their material}
- H10W 72/075: {of bond wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A wiring substrate in which a plating layer is sufficiently plated on a surface metal layer and which has an excellent reliability is provided. A wiring substrate includes an insulating base; a heat dissipation member disposed in the insulating base, the heat dissipation member partially exposed from the insulating base, the heat dissipation member containing Cu; a surface metal layer disposed on a surface of the insulating base, the surface metal layer contacting and covering the heat dissipation member, the surface metal layer containing Mo as a main component, the surface metal layer including a surface portion containing Cu; and a plating layer disposed on the surface metal layer, wherein Cu contained in the heat dissipation member and Cu contained in the surface portion are bonded to each other.

## Claims

### Claim at position 1

-4. (canceled)

### Claim 5

A wiring substrate, comprising:
an insulating base;
a heat dissipation member disposed in the insulating base, the heat dissipation member partially exposed from the insulating base, the heat dissipation member containing Cu;
a surface metal layer disposed on a surface of the insulating base, the surface metal layer contacting and covering the heat dissipation member, the surface metal layer containing Mo as a main component, the surface metal layer comprising a surface portion, the surface portion containing Cu; and
a plating layer disposed on the surface metal layer,
wherein Cu contained in the heat dissipation member and Cu contained in the surface portion are bonded to each other.

### Claim 6 (depends on 5)

The wiring substrate according to claim 5,
wherein the surface metal layer comprises a surface,
the surface comprising:
a first region overlapping the heat dissipation member in a plan view, the first region containing Cu; and
a second region located in a vicinity of the first region, the second region containing Cu, and
wherein, a content rate of Cu in the first region, is larger than a content rate of Cu in the second region.

### Claim 7 (depends on 5)

The wiring substrate according to claim 5,
wherein the surface metal layer comprises an inside portion,
the inside portion comprising:
a third region overlapping the heat dissipation member in a plan view, the third region containing Cu; and
a fourth region located in a vicinity of the third region in a plan view, the fourth region containing Cu, and
wherein a content rate of Cu in the third region is larger than a content rate of Cu in the fourth region.

### Claim 8 (depends on 5)

An electronic device, comprising:
the wiring substrate according to claim 5; and
an electronic component mounted on the wiring substrate.