# US 2014/0196154 A1 · Systems and methods for controlling access to secure debugging and profiling features of a computer system

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- Number: US 2014/0196154 A1
- Document ID: US20140196154A1
- Status: Published application
- Kind: A1
- Application number: 14/179,765
- Filed: 2014-02-13
- Published: 2014-07-10
- Earliest claimed: 2006-05-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Gary L. Swoboda
- Web page: https://patentgrep.com/patent/US20140196154A1

## CPC

- G06F 21/62: Protecting access to data via a platform, e.g. using keys or access control rules
- G06F 11/3656: {using a specific debug interface}
- G06F 21/85: interconnection devices, e.g. bus-connected or in-line devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.

## Claims

### Claim 1

A system comprising:
A. processor circuitry having data leads and debug/profile data leads;
B. test interface circuitry having processor debug/profile leads connected to the debug/profile leads of the processor circuitry and having memory debug/profile leads; and
C. memory circuitry having data leads connected with the data leads of the processor circuitry and having debug/profile data leads connected with the memory debug/profile leads, the memory circuitry maintaining locations for storing data arranged in pages of data and for storing a page attribute table, there being a place in the page attribute table for an attribute for each page of data.

### Claim 2 (depends on 1)

The system of claim 1 in which the memory circuitry includes a memory controller having leads connected to the data leads of the processor circuitry and data memory leads, the memory circuitry including data memory circuitry providing locations for the data, data tag information, and the page attribute table, the data memory circuitry having data memory leads connected to the data memory leads of the memory controller.

### Claim 3 (depends on 1)

The system of claim 1 in which the memory circuitry includes an L1 cache, the L1 cache including a memory controller having leads connected to the data leads of the processor circuitry and data memory leads, the memory circuitry including data memory circuitry providing locations for the data, data tag information, and the page attribute table, the data memory circuitry having data memory leads connected to the data memory leads of the memory controller.