# US 2014/0196045 A1 · Processor and program execution method capable of efficient program execution > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0196045 A1 - Document ID: US20140196045A1 - Status: Published application - Kind: A1 - Application number: 14/203,569 - Filed: 2014-03-11 - Published: 2014-07-10 - Earliest claimed: 2002-01-09 - Assignees: Panasonic Corporation - Applicants: Panasonic Corporation - Inventors: KAZUSHI KURATA; KAZUYA FURUKAWA; TETSUYA TANAKA; NOBUO HIGAKI; KUNIHIKO HAYASHI; HIROSHI KADOTA; TOKUZO KIYOHARA; KOZO KIMURA; HIDESHI NISHIDA; SHIGEKI FUJII; TOSHIO SUGIMURA - Web page: https://patentgrep.com/patent/US20140196045A1 ## CPC - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3867: {using instruction pipelines} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F 9/462: {with multiple register sets} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot. ## Claims ### Claim 1 A processor for executing a plurality of tasks by switching a timeslot and iterating a plurality of timeslots, comprising: a table in which tasks are defined in correspondence with timeslots, wherein in the table, (i) the number of timeslots to be held in one iteration is defined, (ii) for each of the timeslots a total time period during the predetermined number of iterations is designated and, (iii) a plurality of tasks are defined in correspondence with at least one of the timeslots, a timeslot is switched every time a predetermined period elapses, and one task is selected and executed by referring to the table in correspondence with switching of timeslot. ### Claim 2 (depends on 1) The processor of claim 1, wherein at least one part of a task is defined in correspondence with at least one timeslot among the timeslots, and one part of a task is selected and executed by referring to the table in correspondence with switching of timeslot. ### Claim 3 (depends on 1) The processor of claim 1, wherein in the table, if a plurality of tasks are defined in correspondence with one timeslot, priority levels of the plurality of tasks are defined, and one task among the plurality of tasks corresponding to the one timeslot is selected and executed in accordance with the priority levels. ### Claim 4 (depends on 1) The processor of claim 1, further comprising: a task state storage register indicating one or more executable tasks among the plurality of tasks corresponding to the one timeslot, wherein one task among the plurality of tasks corresponding to the one timeslot is executed in accordance with the task state storage register. ### Claim 5 (depends on 4) The processor of claim 4, wherein in the table, if a plurality of tasks are defined in correspondence with one timeslot, priority levels of the plurality of tasks are defined, and one task among the one or more executable tasks indicated by the task state storage register is selected and executed in accordance with the priority levels. ### Claim 6 (depends on 1) The processor of claim 1, wherein the predetermined period is variable. ### Claim 7 (depends on 1) The processor according to claim 1, wherein the predetermined period is assigned to each timeslot. ### Claim 8 (depends on 6) The processor according to claim 6, further comprising: a cycle counter, wherein the timeslot is switched by a signal which is output from the cycle counter and indicates that the predetermined period has elapsed. ### Claim 9 (depends on 1) The processor of claim 1, wherein if the task ends within the predetermined period, another task for a same timeslot as the task is executed. ### Claim 10 (depends on 3) The processor of claim 3, wherein if a first task among the plurality of tasks ends within the predetermined period, a second task for a same timeslot as the first task is executed. ### Claim 11 (depends on 10) The processor of claim 10, wherein the second task is a task having the highest priority level among tasks that have not been executed by the processor. ### Claim 12 (depends on 1) The processor of claim 1, wherein if the task ends within the predetermined period and there is no task in an executable state for a timeslot to be executed next, the timeslot is further switched to a timeslot after next. ### Claim 13 (depends on 1) The processor of claim 1, wherein before an execution of a first task is completed, a context corresponding to a second task, which is to be executed continuously after the first task, is stored into a register group, and the second task is executed from a position indicated by the context stored in the register group. ### Claim 14 (depends on 13) The processor of claim 13, wherein after a timeslot is switched, the second task is executed from the position indicated by the context stored in the register group. ### Claim 15 (depends on 13) The processor of claim 13, wherein in the table, when a plurality of tasks are defined in correspondence with one timeslot, priority levels of the plurality of tasks are defined, and one task is selected in accordance with the priority levels from among the plurality of tasks corresponding to the one timeslot. ### Claim 16 (depends on 13) The processor of claim 13, further comprising: a task state storage register indicating one or more executable tasks among the plurality of tasks corresponding to the one timeslot, wherein one task among the plurality of tasks corresponding to the one timeslot is executed in accordance with the task state storage register. ### Claim 17 (depends on 16) The processor of claim 16, wherein in the table, if a plurality of tasks are defined in correspondence with one timeslot, priority levels of the plurality of tasks are defined, and one task among the plurality of tasks corresponding to the one timeslot is selected and executed in accordance with the priority levels. ### Claim 18 (depends on 1) The processor of claim 1, wherein a task corresponding to the timeslot is executed, and when the task is completed within the predetermined period and there is no task in an executable state for a timeslot to be executed next, a clock-pulse supply to a processing execution unit is blocked. ### Claim 19 (depends on 7) The processor according to claim 7, further comprising: a cycle counter, wherein the timeslot is switched by a signal which is output from the cycle counter and indicates that the predetermined period has elapsed. ### Claim 20 (depends on 5) The processor according to claim 5, wherein the predetermined period is assigned to each timeslot. ### Claim 21 (depends on 20) The processor according to claim 20, further comprising: a cycle counter, wherein the timeslot is switched by a signal which is output from the cycle counter and indicates that the predetermined period has elapsed.