# US 2014/0195999 A1 · Method of designing semiconductor integrated circuit

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- Number: US 2014/0195999 A1
- Document ID: US20140195999A1
- Status: Published application
- Kind: A1
- Application number: 14/206,023
- Filed: 2014-03-12
- Published: 2014-07-10
- Earliest claimed: 2011-09-13
- Assignees: Fujitsu Limited
- Applicants: Fujitsu Limited
- Inventors: Shinichi NAKAMOTO
- Web page: https://patentgrep.com/patent/US20140195999A1

## CPC

- G06F 30/36: Circuit design at the analogue level
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of designing a semiconductor integrated circuit, includes inserting, between a power supply voltage and a ground voltage, at least two types of capacitor cells which have a different ratio, the ratio being between an inverse number of a capacitance value of a capacitative element and a resistance value of an equivalent series resistance, such that an impedance between the power supply voltage and the ground voltage in a resonance frequency according to capacitances of the at least two types of capacitor cells and an external inductance, and an impedance between the power supply voltage and the ground voltage in a target frequency, are near respective desired values or less than or equal to the respective desired values.

## Claims

### Claim 1

A method of designing a semiconductor integrated circuit, comprising:
inserting, between a power supply voltage and a ground voltage, at least two types of capacitor cells which have a different ratio, the ratio being between an inverse number of a capacitance value of a capacitative element and a resistance value of an equivalent series resistance, such that an impedance between the power supply voltage and the ground voltage in a resonance frequency according to capacitances of the at least two types of capacitor cells and an external inductance, and an impedance between the power supply voltage and the ground voltage in a target frequency, are near respective desired values or less than or equal to the respective desired values.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
when generating the at least two types of capacitor cells,
determining a capacitance value of a first capacitative element according to the resonance frequency, the external inductance, and a first desired impedance;
determining a resistance value of an equivalent series resistance of the first capacitative element according to the first desired impedance;
determining a capacitance value of a second capacitative element according to the target frequency and a second desired impedance;
determining a resistance value of an equivalent series resistance of the second capacitative element according to the second desired impedance;
realizing the first capacitative element and the equivalent series resistance of the first capacitative element by connecting one or a plurality of first capacitor cells in parallel among the at least two types of capacitor cells; and
realizing the second capacitative element and the equivalent series resistance of the second capacitative element by connecting one or a plurality of second capacitor cells in parallel among the at least two types of capacitor cells.

### Claim 3 (depends on 2)

The method according to claim 2, further comprising:
determining the capacitance value of the first capacitative element, such that a reactance in the resonance frequency of the first capacitative element is equal to both a reactance of the external inductance in the resonance frequency and the first desired impedance; and
determining the resistance value of the equivalent series resistance of the first capacitative element, to be equal to the first desired impedance.

### Claim 4 (depends on 3)

The method according to claim 3, further comprising:
determining the capacitance value of the second capacitative element, such that a reactance in the target frequency of the second capacitative element is less than or equal to the second desired impedance; and
determining the resistance value of the equivalent series resistance of the second capacitative element, to be less than or equal to the second desired impedance.

### Claim 5

A non-transitory computer-readable recording medium storing a program for designing a semiconductor integrated circuit, wherein the program causes a computer to execute a process comprising:
inserting, between a power supply voltage and a ground voltage, at least two types of capacitor cells which have a different ratio, the ratio being between an inverse number of a capacitance value of a capacitative element and a resistance value of an equivalent series resistance, such that an impedance between the power supply voltage and the ground voltage in a resonance frequency according to capacitances of the at least two types of capacitor cells and an external inductance, and an impedance between the power supply voltage and the ground voltage in a target frequency, are near respective desired values or less than or equal to the respective desired values.

### Claim 6 (depends on 5)

The non-transitory computer-readable recording medium according to claim 5, the process further comprising:
determining a capacitance value of a first capacitative element according to the resonance frequency, the external inductance, and a first desired impedance;
determining a resistance value of an equivalent series resistance of the first capacitative element according to the first desired impedance;
determining a capacitance value of a second capacitative element according to the target frequency and a second desired impedance;
determining a resistance value of an equivalent series resistance of the second capacitative element according to the second desired impedance;
realizing the first capacitative element and the equivalent series resistance of the first capacitative element by connecting one or a plurality of first capacitor cells in parallel among the at least two types of capacitor cells; and
realizing the second capacitative element and the equivalent series resistance of the second capacitative element by connecting one or a plurality of second capacitor cells in parallel among the at least two types of capacitor cells.

### Claim 7 (depends on 6)

The non-transitory computer-readable recording medium according to claim 6, the process further comprising:
determining the capacitance value of the first capacitative element, such that a reactance in the resonance frequency of the first capacitative element is equal to both a reactance of the external inductance in the resonance frequency and the first desired impedance; and
determining the resistance value of the equivalent series resistance of the first capacitative element, to be equal to the first desired impedance.

### Claim 8 (depends on 7)

The non-transitory computer-readable recording medium according to claim 7, the process further comprising:
determining the capacitance value of the second capacitative element, such that a reactance in the target frequency of the second capacitative element is less than or equal to the second desired impedance; and
determining the resistance value of the equivalent series resistance of the second capacitative element, to be less than or equal to the second desired impedance.