# US 2014/0195998 A1 · Automatic Generation of Wire Tag Lists for a Metal Stack > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195998 A1 - Document ID: US20140195998A1 - Status: Published application - Kind: A1 - Application number: 13/737,231 - Filed: 2013-01-09 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Charles J. Alpert; Robert M. Averill, III; Eric J. Fluhr; Zhuo Li; Tuhin Mahmud; Jose L.P. Neves; Stephen T. Quay; Chin Ngai Sze; Yaoguang Wei - Web page: https://patentgrep.com/patent/US20140195998A1 ## CPC - G06F 30/3947: global - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design. ## Claims ### Claim 1 A method, in a data processing system comprising at least one processor and at least one memory, for pruning a layer trait library for use in wire routing in an integrated circuit design process, comprising the following operations performed by the data processing system: receiving a plurality of wirecodes and a metal stack definition; generating a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition; generating a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library; and storing the pruned layer trait library for performing wire routing of an integrated circuit design, wherein generating the pruned layer trait library comprises: pruning the verbose layer trait library to remove redundant layer traits to generate a first pruned layer trait library; performing clustering of layer traits in the first pruned layer trait library; and pruning the first layer trait library based on the clustering of layer traits in the first pruned layer trait library to generate a second pruned layer trait library. ### Claim 2 (depends on 1) The method of claim 1, further comprising performing wire routing of the integrated circuit design based on the stored pruned layer trait library. ### Claim 3 (depends on 2) The method of claim 2, further comprising fabricating an integrated circuit device based on the integrated circuit design, including the wire routing performed based on the stored pruned layer trait library. ### Claim 4 (canceled) ### Claim 5 (depends on 1) The method of claim 1, wherein pruning the verbose layer trait library to remove redundant layer traits comprises: identifying layer traits in the verbose layer trait library having a similar resistance-capacitance (RC) characteristic to generate one or more layer trait groups having a similar RC characteristic; and selecting a representative layer trait from each group of the one or more layer trait groups to represent the layer traits in the group to be included in the first pruned layer trait library. ### Claim 6 (depends on 5) The method of claim 5, wherein the representative layer trait that is selected from each group is selected based on one or more of resource costs associated with the layer traits in the group, delay and timing characteristics of the layer traits in the group, time of flight of layer traits in the group, reach limit of layer traits in the group, coupling timing of traits in the group, or routing cost of layer traits in the group. ### Claim 7 (depends on 1) The method of claim 1, wherein generating the pruned layer trait library further comprises: performing clustering of layer traits in the second pruned layer trait library; and pruning the second pruned layer trait library based on the clustering of layer traits in the second pruned layer trait library to generate a third pruned layer trait library. ### Claim 8 (depends on 7) The method of claim 7, wherein: performing clustering of layer traits in the second pruned layer trait library comprises clustering layer traits according to similar congestion levels such that one or more clusters of layer traits are generated where each cluster has layer traits having a similar congestion level, and pruning the second pruned layer trait library based on the clustering of layer traits in the second pruned layer trait library to generate a third pruned layer trait library comprises pruning each of the clusters in the one or more clusters. ### Claim 9 (depends on 8) The method of claim 8, wherein pruning the second pruned layer trait library based on the clustering of layer traits in the second pruned layer trait library to generate a third pruned layer trait library comprises selecting, from each cluster in the one or more clusters, a representative layer trait from the layer traits of the cluster based on at least one of resource costs or timing and delay characteristics of the layer traits of the cluster. ### Claim 10 (depends on 7) The method of claim 7, further comprising: performing a wire routing process on the integrated circuit design using the first, second, and third pruned layer trait libraries, where each of the first, second, and third pruned layer trait libraries are used at a different granularity of the wire routing process. ### Claim 11 (depends on 10) The method of claim 10, wherein the third pruned layer trait library is used at a coarsest level of granularity of the wire routing process and the first pruned layer trait library is used at a finest level of granularity of the wire routing process. ### Claim 12 (depends on 1) The method of claim 1, wherein the layer traits each comprise a combination of wirecode and layer range. ### Claim 13 A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to: receive a plurality of wirecodes and a metal stack definition; generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition; generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library; and store the pruned layer trait library for performing wire routing of an integrated circuit design, wherein the computer readable program causes the computing device to generate the pruned layer trait library at least by: pruning the verbose layer trait library to remove redundant layer traits to generate a first pruned layer trait library; performing clustering of layer traits in the first pruned layer trait library; and pruning the first layer trait library based on the clustering of layer traits in the first pruned layer trait library to generate a second pruned layer trait library. ### Claim 14 (depends on 13) The computer program product of claim 13, wherein the computer readable program further causes the computing device to perform wire routing of the integrated circuit design based on the stored pruned layer trait library. ### Claim 15 (depends on 14) The computer program product of claim 14, wherein the computer readable program further causes the computing device to control fabrication of an integrated circuit device based on the integrated circuit design, including the wire routing performed based on the stored pruned layer trait library. ### Claim 16 (canceled) ### Claim 17 (depends on 13) The computer program product of claim 13, wherein pruning the verbose layer trait library to remove redundant layer traits comprises: identifying layer traits in the verbose layer trait library having a similar resistance-capacitance (RC) characteristic to generate one or more layer trait groups having a similar RC characteristic; and selecting a representative layer trait from each group of the one or more layer trait groups to represent the layer traits in the group to be included in the first pruned layer trait library. ### Claim 18 (depends on 17) The computer program product of claim 17, wherein the representative layer trait that is selected from each group is selected based on one or more of resource costs associated with the layer traits in the group, delay and timing characteristics of the layer traits in the group, time of flight of layer traits in the group, reach limit of layer traits in the group, coupling timing of traits in the group, or routing cost of layer traits in the group. ### Claim 19 (depends on 13) The computer program product of claim 13, wherein the computer readable program further causes the computing device to generate the pruned layer trait library further at least by: performing clustering of layer traits in the second pruned layer trait library; and pruning the second pruned layer trait library based on the clustering of layer traits in the second pruned layer trait library to generate a third pruned layer trait library. ### Claim 20 (depends on 19) The computer program product of claim 19, wherein: performing clustering of layer traits in the second pruned layer trait library comprises clustering layer traits according to similar congestion levels such that one or more clusters of layer traits are generated where each cluster has layer traits having a similar congestion level, and pruning the second pruned layer trait library based on the clustering of layer traits in the second pruned layer trait library to generate a third pruned layer trait library comprises pruning each of the clusters in the one or more clusters. ### Claim 21 (depends on 20) The computer program product of claim 20, wherein pruning the second pruned layer trait library based on the clustering of layer traits in the second pruned layer trait library to generate a third pruned layer trait library comprises selecting, from each cluster in the one or more clusters, a representative layer trait from the layer traits of the cluster based on at least one of resource costs or timing and delay characteristics of the layer traits of the cluster. ### Claim 22 (depends on 19) The computer program product of claim 19, wherein the computer readable program further causes the computing device to: perform a wire routing process on the integrated circuit design using the first, second, and third pruned layer trait libraries, where each of the first, second, and third pruned layer trait libraries are used at a different granularity of the wire routing process. ### Claim 23 (depends on 22) The computer program product of claim 22, wherein the third pruned layer trait library is used at a coarsest level of granularity of the wire routing process and the first pruned layer trait library is used at a finest level of granularity of the wire routing process. ### Claim 24 (depends on 13) The computer program product of claim 13, wherein the layer traits each comprise a combination of wirecode and layer range. ### Claim 25 An apparatus, comprising: a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to: receive a plurality of wirecodes and a metal stack definition; generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition; generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library; and store the pruned layer trait library for performing wire routing of an integrated circuit design, wherein the instructions cause the processor to generate the pruned layer trait library at least by: pruning the verbose layer trait library to remove redundant layer traits to generate a first pruned layer trait library; performing clustering of layer traits in the first pruned layer trait library; and pruning the first layer trait library based on the clustering of layer traits in the first pruned layer trait library to generate a second pruned layer trait library.