# US 2014/0195996 A1 · Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195996 A1 - Document ID: US20140195996A1 - Status: Published application - Kind: A1 - Application number: 13/526,252 - Filed: 2012-06-18 - Published: 2014-07-10 - Earliest claimed: 2012-06-18 - Assignees: International Business Machines Corporation - Inventors: Pradip Bose; Alper Buyuktosunoglu; John A. Darringer; Moinuddin K. Qureshi; Jeonghee Shin - Web page: https://patentgrep.com/patent/US20140195996A1 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. ## Claims ### Claim 1 A method for integrated circuit (IC) chip and package design and IC chip operation comprising: generating a data structure representing a current distribution relation between one or more current sources within a layout region of said chip, and one or more physical structures that deliver electrical current drawn by said current sources in said layout region as connected via grid networks in said IC; obtaining, using said data structure, an amount of current flow via said physical structures with respect to an amount of current drawn by current sources; and determining, using said current flow and current drawn amounts, locations of blocks having said one or more current sources, with respect to one or more objectives and constraints, said block locations effecting a non-uniform allocation of physical structures to blocks in one IC region than blocks in other regions having like one or more current sources, and, subsequently operating blocks in said regions at current draw activity levels according to the non-uniform allocation, wherein a programmed processor unit performs one or more said generating, obtaining, determining and operating. ### Claim 2 (depends on 1) The method of claim 1, wherein a block includes a central processing unit including one or more cores therein in said layout region. ### Claim 3 (depends on 2) The method of claim 2, wherein a core includes a bus unit, cache memory, fetch unit, decode unit, instruction sequencing unit, execution units such as fixed point unit, floating point unit, load/store unit. ### Claim 4 (depends on 1) The method of claim 1, wherein said block locations effect a non-uniform allocation of physical structures to blocks according to a target power delivery requirement of each said blocks, wherein an allocation of physical structures to grid networks is optimized with respect to different power corners. ### Claim 5 (depends on 2) The method of claim 2, further comprising: scheduling, at an operating system (O/S) or hypervisor of a host system, an application to run at said IC at scheduled times, said application being scheduled for processing at a region of said layout by: allocating applications to cores based on the type of instructions in the workload. ### Claim 6 (depends on 5) The method of claim 5, wherein said scheduling further comprises: scheduling workload or workload operations of a program running at said IC according to the non-uniform allocation of physical structures. ### Claim 7 (depends on 5) The method of claim 5, wherein said scheduling further comprises: scheduling workload or workload operations of a program running on the chip to perform increased power operation levels on a core in regions having a greater amount of physical structures allocated as compared to power operation levels at a core in regions having less physical structures allocated. ### Claim 8 (depends on 7) The method of claim 7, wherein said scheduling further comprises: scheduling workload or workload operations to cores based on the type of instructions in the application. ### Claim 9 (depends on 7) The method of claim 7, wherein a core includes a cache memory unit, said operating said core at said increased power operation level comprising: operating said core at a higher clock frequency compared to nominal clock frequency, utilizing one or more cache memory units from other cores, or both operating said core at said higher clock frequency and utilizing caches of other cores in regions having less amount of physical structures allocated. ### Claim 10 (depends on 1) The method of claim 1, wherein said (IC) is a 3-Dimensional or of a stacked chip architecture, said blocks having current sources being located on separate physical layers of a stacked arrangement, or displaced horizontally from each other on a common carrier. ### Claim 11 A system for integrated circuit (IC) chip and package design and IC chip operation comprising: a computer system including a memory storage device and a programmed processor unit in communication with said memory storage device, said programmed processor unit configured to: generate a data structure representing a current distribution relation between one or more current sources within a layout region of said chip, and one or more physical structures that deliver electrical current drawn by said current sources in said layout region as connected via grid networks in said IC; obtain, using said data structure, an amount of current flow via said physical structures with respect to an amount of current drawn by current sources; and determine, using said current flow and current drawn amounts, locations of blocks having said one or more current sources, with respect to one or more objectives and constraints, said block locations effecting a non-uniform allocation of physical structures to blocks in one IC region than blocks in other regions having like one or more current sources, and, subsequently operate blocks in said regions at current draw activity levels according to the non-uniform allocation, wherein a programmed processor unit performs one or more said generating, obtaining, determining and operating. ### Claim 12 (depends on 11) The system as claimed in claim 11, wherein a block includes a central processing unit including one or more cores therein in said layout region, ### Claim 13 (depends on 12) The system as claimed in claim 12, wherein a core includes a bus unit, cache memory, fetch unit, decode unit, instruction sequencing unit, execution units such as fixed point unit, floating point unit, load/store unit. ### Claim 14 (depends on 11) The system as claimed in claim 11, wherein said block locations effect a non-uniform allocation of physical structures to blocks according to a target power delivery requirement to said blocks, wherein an allocation of physical structures to grid networks is optimized with respect to different power corners. ### Claim 15 (depends on 12) The system as claimed in claim 12, further comprising: scheduling, at an operating system (O/S) or hypervisor of a host system, an application to run at said IC at scheduled times, said application being scheduled for processing at a region of said layout by: allocating applications to cores based on the type of instructions in the workload. ### Claim 16 (depends on 15) The system as claimed in claim 15, further comprising: scheduling workload or workload operations of a program running at said IC according to the non-uniform allocation of physical structures. ### Claim 17 (depends on 15) The system as claimed in claim 15, further comprising: scheduling workload or workload operations of a program running on the chip to perform increased power operations on a core in regions having a greater amount of physical structures allocated as compared to power operation levels at a core in regions having less physical structures allocated. ### Claim 18 (depends on 17) The system as claimed in claim 17, further comprising: scheduling workload or workload operations to cores based on the type of instructions in the application. ### Claim 19 (depends on 17) The system as claimed in claim 17, wherein a core includes a cache memory unit, said operating said core at said higher power operations comprising: operating said core at a higher clock frequency compared to nominal clock frequency, utilizing one or more cache memory units from other cores, or both operating said core at said higher clock frequency and utilizing caches of other cores in regions having less amount of physical structures allocated. ### Claim 20 A computer program product for integrated circuit (IC) chip and IC chip operation, the computer program product comprising a tangible storage medium readable by a processing circuit and storing instructions run by the processing circuit for performing a method, the method comprising: generating a data structure representing a current distribution relation between one or more current sources within a layout region of said chip, and one or more physical structures that deliver electrical current drawn by said current sources in said layout region as connected via grid networks in said IC; obtaining, using said data structure, an amount of current flow via said physical structures with respect to an amount of current drawn by current sources; and determining, using said current flow and current drawn amounts, locations of blocks having said one or more current sources, with respect to one or more objectives and constraints, said block locations effecting a non-uniform allocation of physical structures to blocks in one IC region than blocks in other regions having like one or more current sources, and, subsequently operating blocks in said regions at current draw activity levels according to the non-uniform allocation, wherein a programmed processor unit performs one or more said generating, obtaining, determining and operating. ### Claim 21 (depends on 20) The computer program product of claim 20, wherein a block includes a central processing unit including one or more cores therein in said layout region. ### Claim 22 (depends on 20) The computer program product of claim 20, wherein said block locations effect a non-uniform allocation of physical structures to blocks according to a target power delivery requirement of each said blocks, wherein an allocation of physical structures to grid networks is optimized with respect to different power corners.