# US 2014/0195995 A1 · Systems and methods for single cell product path delay analysis

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- Number: US 2014/0195995 A1
- Document ID: US20140195995A1
- Status: Published application
- Kind: A1
- Application number: 13/735,392
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: International Business Machines Corporation
- Inventors: Jeanne P. Bickford; Peter A. Habitz; Vikram Iyengar; Brian A. Worth; Jinjun Xiong
- Web page: https://patentgrep.com/patent/US20140195995A1

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/3312: Timing analysis
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

## Claims

### Claim 1

A method, comprising:
designing a product using a model from an initial test site;
creating performance path tests for one or more paths on the product;
measuring performance path parameters of the product; and
determining that the measured performance path parameters match predicted performance path parameters.

### Claim 2 (depends on 1)

The method of claim 1, wherein the product comprises structures used to conduct parametric measurements.

### Claim 3 (depends on 1)

The method of claim 1, wherein the creating the performance path tests comprises determining at least one of a path delay and a frequency of a selected path as a function of a process window sigma for the at least one of the path delay and the frequency.

### Claim 4 (depends on 3)

The method of claim 3, wherein the determining at least one of the path delay and the frequency of a selected path as a function of a process window sigma provides the expected performance path parameters.

### Claim 5 (depends on 1)

The method of claim 1, further comprising determining a process window sigma for each die of the product.

### Claim 6 (depends on 1)

The method of claim 1, wherein the determining that the measured performance path parameters match predicted performance path parameters comprises:
conducting a regression analysis;
inputting identified sensitivity input into a canonical model; and
comparing the regression analysis with a timing analysis.

### Claim 7 (depends on 6)

The method of claim 6, wherein the comparing the regression analysis with the timing analysis comprises comparing chip parameter sensitivities with a timing methodology.

### Claim 8 (depends on 7)

The method of claim 7, wherein the chip parameter sensitivities comprise both process parameters and environmental parameters including temperature, voltage, and aging.

### Claim 9 (depends on 8)

The method of claim 8, wherein the chip parameter sensitivities are measured in sigmas of a distribution.

### Claim 10

A method, comprising:
establishing a path selection to test;
determining a process corner for each chip;
measuring at least one of a path delay and a frequency of each chip;
comparing data sensitivities based on a regression analysis with timing sensitivities; and
adjusting a timing margin setting based on the comparison of the data sensitivities and the timing sensitivities.

### Claim 11 (depends on 10)

The method of claim 10, wherein path selection criteria to select the path to test comprises timing sensitivities of device components and path properties.

### Claim 12 (depends on 10)

The method of claim 10, wherein the determining a process corner for each chip comprises determining a value of a parameter setting for each chip to be tested.

### Claim 13 (depends on 10)

The method of claim 10, wherein qualification criteria of a selected path comprises at least one of voltages across an allowed operation range and temperatures across an allowed operation range.

### Claim 14 (depends on 10)

The method of claim 10, wherein a selected path to be tested can be compared to one or more other paths to determine which device sensitivities occur on the selected path.

### Claim 15 (depends on 10)

The method of claim 10, further comprising marginalizing data sensitivities that exceed a predetermined threshold of the timing sensitivities.

### Claim 16 (depends on 10)

The method of claim 10, further comprising monitoring a timing sensitivity delta of the timing sensitivities, such that a timing methodology does not damage special paths.

### Claim 17

A computer system for qualifying a performance path, the system comprising:
a CPU, a computer readable memory and a computer readable storage media;
first program instructions to create performance path tests for one or more paths on a product;
second program instructions to measure performance path parameters of the product;
third program instructions to determine that the measured performance path parameters match predicted performance path parameters; and
fourth program instructions to adjust a timing margin setting when the measured performance path parameters do not match the predicted performance path parameters,
wherein the first, second, third, and fourth program instructions are stored on the computer readable storage media for execution by the CPU via the computer readable memory.

### Claim 18 (depends on 17)

The computer system of claim 17, wherein the creating the performance path tests comprises determining at least one of a path delay and a frequency of a selected path as a function of a process window sigma for the at least one of a path delay and a frequency.

### Claim 19 (depends on 18)

The computer system of claim 18, wherein the determining that the measured performance path parameters match predicted performance path parameters comprises:
conducting a regression analysis;
inputting identified sensitivity input into a canonical model; and
comparing the regression analysis with a timing analysis.

### Claim 20 (depends on 19)

The computer system of claim 19, further comprising fifth program instructions to marginalize data sensitivities that exceed a predetermined threshold of timing sensitivities of the one or more paths.