# US 2014/0195880 A1 · Rate matching and scrambling techniques for control signaling

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0195880 A1
- Document ID: US20140195880A1
- Status: Published application
- Kind: A1
- Application number: 14/194,430
- Filed: 2014-02-28
- Published: 2014-07-10
- Earliest claimed: 2007-07-06
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: BADRI N. VARADARAJAN; Xiaomeng Shi; Eko Nugroho Onggosanusi
- Web page: https://patentgrep.com/patent/US20140195880A1

## CPC

- H04L 27/2626: {Arrangements specific to the transmitter only}
- H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms}
- H04L 1/0067: {Rate matching (H04L1/0013 and H04L1/08 take precedence)}
- H04L 1/0072: {Error control for data other than payload data, e.g. control data}
- H04L 1/0013: {Rate matching, e.g. puncturing or repetition of code symbols}
- H04L 1/0046: {Code rate detection or code type detection (H04L1/0038 takes precedence; detection of the data rate H04L25/0262; for packet format H04L1/0091)}
- H04L 1/0065: {Serial concatenated codes}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits. Additionally, the transmitter also includes an encoding module configured to perform forward error correction encoding and rate matching on the scrambled bits to obtain a required number of control channel output bits, and a transmit module configured to transmit the control channel output bits for one or more control channels.

## Claims

### Claim at position 1

1-24. (canceled)

### Claim 25

A receiver comprising:
a control signal receiving module configured to extract soft information on received control signal bits for one or more control channels;
a rate de-matching and forward error correction decoding module configured to process the soft information to obtain a set of decoded bits;
a descrambling module configured to apply a masking sequence to one or more of the decoded bits to provide a set of unmasked bits; and
a payload extraction and padding-check module configured to test validity of at least one of the payload bits and padding bits from the unmasked bits.

### Claim 26 (depends on 25)

The receiver as recited in claim 25 wherein the padding check module declares validity if the padding bits are equal to a CRC computed on the payload bits.

### Claim 27 (depends on 26)

The receiver as recited in claim 26 wherein the padding-check module tests two or more payload lengths for the same number of unmasked bits corresponding to two or more CRC lengths.

### Claim 28 (depends on 25)

The receiver as recited in claim 25 wherein the padding-check module declares validity if a portion of the padding bits is obtained by a linear code operating on the payload bits and a remaining portion of the padding bits is obtained by a CRC operating on a combination of the portion of padding bits and the payload bits.

### Claim 29 (depends on 25)

The receiver as recited in claim 25 wherein the padding-check module declares validity if a portion of the padding bits is obtained by a CRC operating on the payload bits and a remaining portion of the padding bits is obtained by a linear code operating on the CRC bits.

### Claim 30 (depends on 25)

The receiver as recited in claim 25 wherein the padding-check module declares validity if a portion of the padding bits is obtained by a CRC operating on the payload bits and a remaining portion of the padding bits is obtained by a linear code operating on a combination of the payload and CRC bits.

### Claim 31 (depends on 25)

The receiver as recited in claim 25 wherein the masking sequence for a control channel is obtained by a linear code operating on an identification number corresponding to the control channel.

### Claim 32 (depends on 31)

The receiver as recited in claim 31 wherein the masking sequence is obtained by appending one or more padding bits to the identification number where at least one of the padding bits is derived from the bits of the identification number.

### Claim 33 (depends on 25)

The receiver as recited in claim 25 wherein the masking sequence for a control channel is a function of a combination of an identification number corresponding to the control channel and a length of the control channel output bits.

### Claim 34 (depends on 25)

The receiver as recited in claim 25 wherein the masking sequence for a control channel is an output of a linear shift register having a seed and a shift register polynomial.

### Claim 35 (depends on 34)

The receiver as recited in claim 34 wherein the seed of the linear shift register for the control channel is obtained by padding an identification number corresponding to the control channel.

### Claim 36 (depends on 34)

The receiver as recited in claim 34 wherein the shift register polynomial for the control channel is a function of the number of control channel output bits.

### Claim 37

A method of operating a receiver comprising:
extracting soft information on received control signal bits for one or more control channels;
processing the soft information for the control channel to obtain a set of decoded bits;
applying a masking sequence to one or more of the decoded bits to provide a set of unmasked bits; and
testing validity of at least one of the payload bits and padding bits from the unmasked bits employing a padding-check module.

### Claim 38 (depends on 37)

The method as recited in claim 37 wherein the padding check module declares validity if the padding bits are equal to a CRC computed on the payload bits.

### Claim 39 (depends on 37)

The method as recited in claim 37 wherein the padding-check module tests two or more payload lengths for the same number of unmasked bits corresponding to two or more CRC lengths.

### Claim 40 (depends on 37)

The method as recited in claim 37 wherein the padding-check module declares validity if a portion of the padding bits is obtained by a linear code operating on the payload bits and a remaining portion of the padding bits is obtained by a CRC operating on a combination of the portion of padding bits and the payload bits.

### Claim 41 (depends on 37)

The method as recited in claim 37 wherein the padding-check module declares validity if a portion of the padding bits is obtained by a CRC operating on the payload bits and a remaining portion of the padding bits is obtained by a linear code operating on the CRC hits.

### Claim 42 (depends on 37)

The method as recited in claim 37 wherein the padding-check module declares validity if a portion of the padding bits is obtained by a CRC operating on the payload bits and a remaining portion of the padding bits is obtained by a linear code operating on a combination of the payload and CRC bits.

### Claim 43 (depends on 37)

The method as recited in claim 37 wherein the masking sequence for a control channel is obtained by a linear code operating on an identification number corresponding to the control channel.

### Claim 44 (depends on 43)

The method as recited in claim 43 wherein the masking sequence is obtained by appending one or more padding bits to the identification number where at least one of the padding bits is derived from the bits of the identification number.

### Claim 45 (depends on 37)

The method as recited in claim 37 wherein the masking sequence for a control channel is a function of a combination of an identification number corresponding to the control channel and a length of the control channel output bits.

### Claim 46 (depends on 37)

The method as recited in claim 37 wherein the masking sequence for a control channel is an output of a linear shift register having a seed and a shift register polynomial.

### Claim 47 (depends on 46)

The method as recited in claim 46 wherein the seed of the linear shift register for the control channel is obtained by padding an identification number corresponding to the control channel.

### Claim 48 (depends on 46)

The method as recited in claim 46 wherein the shift register polynomial for the control channel is a function of the number of control channel output bits.