# US 2014/0195876 A1 · Memory Module Architecture

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- Number: US 2014/0195876 A1
- Document ID: US20140195876A1
- Status: Published application
- Kind: A1
- Application number: 13/993,506
- Filed: 2011-12-28
- Published: 2014-07-10
- Earliest claimed: 2011-12-28
- Assignees: Intel Corporation
- Inventors: Murugasamy K. Nachimuthu; Mohan J. Kumar; Debaleena Das; Dimitrios Ziakas
- Web page: https://patentgrep.com/patent/US20140195876A1

## CPC

- G06F 11/1044: {with specific ECC/EDC distribution}
- G06F 11/1064: {in cache or content addressable memories}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.

## Claims

### Claim 1

A method comprising:
enabling a memory integrated circuit to store data with error correcting code;

### Claim 2 (depends on 1)

The method of claim 1 including forming a memory module including a plurality of memory integrated circuits each to store data with error correcting code.

### Claim 3 (depends on 2)

The method of claim 2 including forming said memory module with an exclusive OR circuit.

### Claim 4 (depends on 2)

The method of claim 2 including enabling the module to be read by accessing data and error correcting code in the same memory access.

### Claim 5 (depends on 4)

The method of claim 4 including accessing the plurality of memory circuits at the same time.

### Claim 6 (depends on 5)

The method of claim 5 including separating data and error correcting code.

### Claim 7 (depends on 2)

The method of claim 2 including providing more memory integrated circuits in said module than are needed to store one cache line of data.

### Claim 8 (depends on 1)

The method of claim 1 including enabling a phase change memory integrated circuit to store data with error correcting code.

### Claim 9

A non-transitory computer readable medium storing instructions to enable a processor to store data with error correcting code in a memory integrated circuit.

### Claim 10 (depends on 9)

The medium of claim 9 further storing instructions to store data with error correcting code in a memory module including a plurality of memory integrated circuits.

### Claim 11 (depends on 10)

The medium of claim 10 further storing instructions to store data with error correcting code in a memory module with an exclusive OR circuit.

### Claim 12 (depends on 10)

The medium of claim 10 further storing instructions to enable the module to be read by accessing data and error correcting code in the same memory access.

### Claim 13 (depends on 12)

The medium of claim 12 further storing instructions to access the plurality of memory circuits at the same time.

### Claim 14 (depends on 13)

The medium of claim 13 further storing instructions to separate data and error correcting code.

### Claim 15 (depends on 9)

The medium of claim 9 further instructions to enable a phase change memory integrated circuit to store data with error correcting code.

### Claim 16

An apparatus comprising:
a memory integrated circuit; and
a controller, coupled to said circuit to store data with error correcting code in a memory integrated circuit.

### Claim 17 (depends on 16)

The apparatus of claim 16 including a memory module including a plurality of memory integrated circuits each to store data with error correcting code.

### Claim 18 (depends on 17)

The apparatus of claim 17 said memory module including an exclusive OR circuit.

### Claim 19 (depends on 17)

The apparatus of claim 17 said module readable by accessing data and error correcting code in the same memory access.

### Claim 20 (depends on 19)

The method of claim 19 said plurality of memory integrated circuits being accessible at the same time.

### Claim 21 (depends on 20)

The apparatus of claim 20 said controller to separate data and error correcting code.

### Claim 22 (depends on 17)

The apparatus of claim 17 said module including more memory integrated circuits than are needed to store one cache line of data.

### Claim 23 (depends on 17)

The apparatus of claim 17 said module including a phase change memory integrated circuit to store data with error correcting code.

### Claim 24

A non-transitory computer readable medium storing instructions to enable a processor to read data and error correcting code from a memory integrated circuit in one read access.

### Claim 25 (depends on 24)

The medium of claim 24 further storing instructions to store data with error correcting code in a memory module including a plurality of memory integrated circuits.

### Claim 26 (depends on 25)

The medium of claim 25 further storing instructions to store data with error correcting code in a memory module with an exclusive OR circuit.

### Claim 27 (depends on 25)

The medium of claim 25 further storing instructions to enable the module to be read by accessing data and error correcting code in the same memory access.

### Claim 28 (depends on 27)

The medium of claim 27 further storing instructions to access the plurality of memory circuits at the same time.