# US 2014/0195869 A1 · Serial i/o using jtag tck and tms signals

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- Number: US 2014/0195869 A1
- Document ID: US20140195869A1
- Status: Published application
- Kind: A1
- Application number: 14/158,365
- Filed: 2014-01-17
- Published: 2014-07-10
- Earliest claimed: 2004-02-17
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20140195869A1

## CPC

- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/28: Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00})
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 13/287: {Multiplexed DMA (G06F13/30 takes precedence)}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- H03K 19/017509: {Interface arrangements}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

## Claims

### Claim 1

An integrated circuit comprising:
A. functional circuitry;
B test data leads including a test data in lead and a test data out lead;
C. control leads including a test clock lead, and a test mode select lead;
D. test circuitry coupled to the functional circuitry and coupled to the test data leads and the control leads, the test circuitry including:
i. first data path circuitry conveying test data to and from the functional circuitry over the test data leads;
ii. second data path circuitry conveying test data to and from the functional circuitry over only the control leads; and
iii. gating circuitry coupled to the first data path circuitry and the second data path circuitry and selecting the second data path circuitry to convey test data to and from the functional circuitry.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which:
A. the first data path circuitry includes test access port circuitry having a test data in input coupled to the test data in lead, a test data out output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the test access port having first data connections with the functional circuitry; and
B. the second data path circuitry includes a serial communication circuit having data and clock connections with the test clock lead and the test mode select lead, the serial communication circuit having second data connections with the functional circuitry separate from the first data connections.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the first data path conveys data to and from the functional circuitry on the test data in lead and the test data out lead using a clock signal received on the test clock lead and a mode select signal received on the test mode select lead.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 in which the second data path conveys data to and from the functional circuitry on the test clock lead using a clock signal received on the test mode select lead.

### Claim 5 (depends on 1)

The integrated circuit of claim 1 in which the first and second data paths have separate connections with the functional circuitry.