# US 2014/0195867 A1 · Memory testing with selective use of an error correction code decoder

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- Number: US 2014/0195867 A1
- Document ID: US20140195867A1
- Status: Published application
- Kind: A1
- Application number: 13/734,334
- Filed: 2013-01-04
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Marc A. Gollub; Girisankar Paulraj; Diyanesh B. Vidyapoornachary; Kenneth L. Wright
- Web page: https://patentgrep.com/patent/US20140195867A1

## CPC

- G11C 29/42: using error correcting codes [ECC] or parity check
- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/56: External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.

## Claims

### Claim 1

A method comprising:
in response to receiving a test activation request indicating a memory location of
a memory device:
directing an access of the memory location to an error correction code (ECC) decoder;
writing a test pattern to the memory location;
reading a value from the memory location; and
determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.

### Claim 2 (depends on 1)

The method of claim 1, wherein the memory location is a byte.

### Claim 3 (depends on 1)

The method of claim 1, further comprising restoring data to the memory location in response to determining that the fault is not detected.

### Claim 4 (depends on 1)

The method of claim 1, further comprising placing a chip mark associated with a dynamic random-access memory (DRAM) including the memory location in response to receiving the test activation request.

### Claim 5 (depends on 4)

The method of claim 4, wherein writing the test pattern comprises writing to a rank, wherein the rank includes the DRAM.

### Claim 6 (depends on 4)

The method of claim 4, further comprising removing the chip mark associated with the DRAM in response to determining that the fault is not detected.

### Claim 7 (depends on 1)

The method of claim 1, wherein the test activation request includes an error indication.

### Claim 8 (depends on 1)

The method of claim 1, wherein the access is a read access or a write access.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
in response to determining that the fault is not detected:
determining an upper delay margin of a first dynamic random-access memory (DRAM) associated with the memory location; and
determining a lower delay margin of the first DRAM.

### Claim 10 (depends on 9)

The method of claim 9, wherein determining the upper delay margin comprises successively incrementing a delay setting associated with the first DRAM, writing the test pattern to the memory location, and reading the value from the memory location, until after a particular increment a comparison of the test pattern and the value indicates that the fault is detected.

### Claim 11 (depends on 9)

The method of claim 9, wherein determining the lower delay margin comprises successively decrementing a delay setting associated with the first DRAM, writing the test pattern to the memory location, and reading the value from the memory location, until after a particular decrement a comparison of the test pattern and the value indicates that the fault is detected.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
determining a delay setting in between the upper delay margin and the lower delay margin;
determining whether a difference between the upper delay margin and the lower delay margin is below a threshold;
in response to determining that the difference is equal to or above the threshold, restoring data to the memory location; and
in response to determining that the difference is below the threshold, maintaining a chip mark on the first DRAM, using a second DRAM instead of the first DRAM, generating a warning regarding the first DRAM, or any combination thereof.

### Claim 13

A system comprising:
a rank including a dynamic random-access memory (DRAM);
an error correction code (ECC) decoder configured to:
detect an error at a memory location of the DRAM; and
in response to detecting the error, place a chip mark associated with the DRAM;
firmware configured to:
detect the chip mark associated with the DRAM;
direct an access of the DRAM to the ECC decoder while the chip mark associated with the DRAM is in place; and
request a self-test engine to perform a test of the memory location; and
the self-test engine configured to:
write to the rank including writing a test pattern to the memory location;
read from the rank including reading a value from the memory location; and
determine whether a fault is detected at the memory location based on a comparison of the value and the test pattern.

### Claim 14 (depends on 13)

The system of claim 13, wherein the firmware is further configured to:
in response to determining that the fault is not detected:
restore data at the memory location; and
remove the chip mark associated with the DRAM.

### Claim 15 (depends on 13)

The system of claim 13, wherein the firmware is further configured to, in response to determining that the fault is detected, maintain the chip mark associated with the DRAM in place.

### Claim 16

A computer-readable medium storing instructions that, when executed by a processor, cause the processor to:
in response to receiving a test activation request indicating a memory location:
direct an access of the memory location to an error correction code (ECC) decoder;
write a test pattern to the memory location;
read a value from the memory location; and
determine whether a fault is detected at the memory location based on a comparison of the test pattern and the value.

### Claim 17 (depends on 16)

The computer-readable medium of claim 16, wherein the access is a read access or a write access.

### Claim 18 (depends on 16)

The computer-readable medium of claim 16, further comprising:
in response to determining that the fault is not detected:
determining an upper delay margin of a dynamic random-access memory (DRAM) associated with the memory location; and
determining a lower delay margin of the DRAM.

### Claim 19 (depends on 18)

The computer-readable medium of claim 18, wherein determining the upper delay margin comprises successively incrementing a delay setting associated with the memory location, writing the test pattern to the memory location, and reading the value from the memory location, until after a particular increment a comparison of the test pattern and the value indicates that the fault is detected.

### Claim 20 (depends on 18)

The computer-readable medium of claim 18, wherein determining the lower delay margin comprises successively decrementing a delay setting associated with the memory location, writing the test pattern to the memory location, and reading the value from the memory location, until after a particular decrement a comparison of the test pattern and the value indicates that the fault is detected.