# US 2014/0195866 A1 · Determining Worst-Case Bit Patterns Based Upon Data-Dependent Jitter

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- Number: US 2014/0195866 A1
- Document ID: US20140195866A1
- Status: Published application
- Kind: A1
- Application number: 14/149,806
- Filed: 2014-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Mentor Graphics Corporation
- Applicants: Mentor Graphics Corporation
- Inventors: Vladimir Dmitriev-Zdorov
- Web page: https://patentgrep.com/patent/US20140195866A1

## CPC

- G01R 31/00: Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00})
- G01R 31/3171: {BER [Bit Error Rate] test}
- H04L 1/00: Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)}
- H04L 1/203: {Details of error rate determination, e.g. BER, FER or WER}
- H04L 1/205: {jitter monitoring}
- G01R 31/31709: {Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements.

## Claims

### Claim at position 1

1-6. (canceled)

### Claim 7

A method comprising:
identifying, by a computing system, data-dependent jitter and a step response associated with a channel;
deriving, by the computing system, a sequence pattern for input into the channel based, at least in part, on the data-dependent jitter and the step response associated with the channel; and
determining, by the computing system, a bit error rate for the channel based, at least in part, on the sequence pattern.

### Claim 8 (depends on 7)

The method of claim 7, wherein deriving the sequence pattern further comprises:
preparing a structure of connected elements;
determining paths through the connected elements in the structure based, at least in part, on jitter samples associated with the data-dependent jitter; and
building the sequence pattern based on the paths through the connected elements.

### Claim 9 (depends on 8)

The method of claim 8, wherein deriving the sequence pattern further comprises building an indexed table of the jitter samples, wherein the structure of the connected elements is prepared based on the indexed table of the jitter samples.

### Claim 10

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
identifying data-dependent jitter and a step response associated with a channel;
deriving a sequence pattern for input into the channel based, at least in part, on the data-dependent jitter and the step response associated with the channel; and
determining a bit error rate for the channel based, at least in part, on the sequence pattern.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein deriving the sequence pattern further comprises:
preparing a structure of connected elements;
determining paths through the connected elements in the structure based, at least in part, on jitter samples associated with the data-dependent jitter; and
building the sequence pattern based on the paths through the connected elements.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein deriving the sequence pattern further comprises building an indexed table of the jitter samples, wherein the structure of the connected elements is prepared based on the indexed table of the jitter samples.