# US 2014/0195852 A1 · Memory testing of three dimensional (3d) stacked memory

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- Number: US 2014/0195852 A1
- Document ID: US20140195852A1
- Status: Published application
- Kind: A1
- Application number: 13/737,063
- Filed: 2013-01-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Marc A. Gollub; Girisankar Paulraj; Diyanesh B. Vidyapoornachary; Kenneth L. Wright
- Web page: https://patentgrep.com/patent/US20140195852A1

## CPC

- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die layer of the DRAM stack. The method further includes sending a request to a test engine to test the first DRAM die layer after writing the data to the second DRAM die layer.

## Claims

### Claim 1

A method comprising:
reading, at a memory controller, first data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack comprising a plurality of stacked DRAM die layers;
writing the first data to a second DRAM die layer of the DRAM stack; and
after writing the first data to the second DRAM die layer, sending a first request to a test engine to test the first DRAM die layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising reading the first data in response to detecting a chip mark associated with the first DRAM die layer;

### Claim 3 (depends on 2)

The method of claim 2, wherein the chip mark may be placed by firmware based on a periodic health check, by an error correction code (ECC) decoder in response to detecting an error, or both.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first request to the test engine includes a mode register set (MRS) command indicating the first DRAM die layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the MRS command indicates a particular memory location of the first DRAM die layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising sending a second request to the test engine to direct an access by the memory controller of the first DRAM die layer to the second DRAM die layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the second request to the test engine includes a mode register set (MRS) command indicating the first DRAM die layer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising removing a chip mark associated with the first DRAM die layer after writing the first data to the second DRAM die layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising receiving a result of testing the first DRAM die layer from the test engine, the result indicating whether a fault is detected at the first DRAM die layer.

### Claim 10 (depends on 9)

The method of claim 9, further comprising reading the result from a register associated with the test engine.

### Claim 11 (depends on 9)

The method of claim 9, wherein the result indicates whether a fault is detected at a particular memory location of the first DRAM die layer.

### Claim 12 (depends on 9)

The method of claim 9, further comprising, in response to the result indicating that a fault is not detected at the first DRAM die layer, sending a second request to the test engine to direct an access by the memory controller of the second DRAM die layer to the first DRAM die layer.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
in response to the result indicating that a fault is not detected at the first DRAM die layer:
reading second data from the second DRAM die layer; and
writing the second data to the first DRAM die layer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising removing a chip mark associated with the first DRAM die layer after writing the second data to the first DRAM die layer.

### Claim 15 (depends on 9)

The method of claim 9, further comprising determining that the second DRAM die layer is unavailable for use as a spare DRAM die layer in response to the result indicating that a fault is detected at the first DRAM die layer.

### Claim 16

An apparatus comprising:
a dynamic random-access memory (DRAM) stack that includes:
a first DRAM die layer; and
a logic DRAM die layer comprising logic configured to:
receive a request to test the first DRAM die layer;
perform testing of the first DRAM die layer in response to the request; and
generate a result of testing the first DRAM die layer, wherein the result indicates whether a fault was detected at the first DRAM die layer.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the result of testing the first DRAM die layer includes a mode register set (MRS) command indicating whether a fault is detected at a particular memory location of the first DRAM die layer.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the first DRAM die layer has a length of one byte and wherein the particular memory location includes an upper nibble on the first DRAM die layer or a lower nibble on the first DRAM die layer.

### Claim 19

A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to:
read first data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack comprising a plurality of stacked DRAM die layers;
write the first data to a second DRAM die layer of the DRAM stack; and
after writing the first data to the second DRAM die layer, send a first request to a test engine to test the first DRAM die layer.

### Claim 20 (depends on 19)

The computer-readable storage medium of claim 19, further comprising instructions that, when executed by the processor, cause the processor to read a result of testing the first DRAM die layer from a register.