# US 2014/0195837 A1 · Enhanced dynamic memory management with intelligent current/power consumption minimization

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- Number: US 2014/0195837 A1
- Document ID: US20140195837A1
- Status: Published application
- Kind: A1
- Application number: 13/736,268
- Filed: 2013-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: QUALCOMM Incorporated
- Applicants: Qualcomm Incorporated
- Inventors: Hee Jun Park; Richard Gerard Hofmann; Yong Ju Lee
- Web page: https://patentgrep.com/patent/US20140195837A1

## CPC

- G06F 1/3225: of memory devices
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 13/1668: {Details of memory controller}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.

## Claims

### Claim 1

An electronic device, comprising:
a plurality of volatile memory devices; and
a processing circuit coupled to the plurality of volatile memory devices, wherein the processing circuit is configured to perform dynamic memory management by
obtaining a low-power state current/power consumption for each volatile memory device in the plurality of volatile memory devices;
copying data from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower low-power state current/power consumption than the first set of volatile memory devices; and
placing the first set of volatile memory devices into a power-down state to reduce power consumption.

### Claim 2 (depends on 1)

The device of claim 1, wherein the processing circuit is further configured to:
determine when to switch the first set of volatile memory devices into the power-down state after a period of inactivity.

### Claim 3 (depends on 1)

The device of claim 1, wherein the low-power state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

### Claim 4 (depends on 1)

The device of claim 1, wherein the processing circuit is further configured to:
place the second set of volatile memory devices into a power conservation state to reduce power consumption.

### Claim 5 (depends on 4)

The device of claim 4, wherein the power conservation state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

### Claim 6 (depends on 4)

The device of claim 4, wherein the low-power state is the power conservation state.

### Claim 7 (depends on 1)

The device of claim 1, wherein the low-power state current/power consumption includes leakage current/power consumption and dynamic power consumption.

### Claim 8 (depends on 1)

The device of claim 1, wherein the plurality of volatile memory devices are arranged in one or more channels, and the first set and second set of volatile memory devices are determined on a per channel basis.

### Claim 9 (depends on 8)

The device of claim 8, wherein the data is copied between memory devices in the same channel.

### Claim 10 (depends on 1)

The device of claim 1, wherein the low-power state current/power consumption for each of the plurality of volatile memory devices is ascertained during a manufacturing stage or during an initialization stage.

### Claim 11 (depends on 1)

The device of claim 1, further comprising:
a power management device coupled to the processing circuit and configured to ascertain the low-power state current/power consumption for each of the plurality of volatile memory devices.

### Claim 12 (depends on 1)

The device of claim 1, wherein the processing circuit is further configured to
compensate for temperature variations between the memory devices; and
normalize the low-power state current/power consumption for each of the plurality of volatile memory devices based on their corresponding temperatures.

### Claim 13 (depends on 1)

The device of claim 1, further comprising:
a non-volatile storage device coupled to the processing circuit, the non-volatile storage device storing the low-power state current/power consumption for each of the plurality of volatile memory devices.

### Claim 14 (depends on 1)

The device of claim 1, wherein the processing circuit is further configured to perform dynamic memory management by
obtaining a low-power state current/power consumption for each memory bank within each of the volatile memory devices of the plurality of volatile memory devices;
copying data from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower low-power state current/power consumption than the first set of memory banks; and
placing the first set of memory banks into a power-down state.

### Claim 15

A method for performing dynamic memory management, comprising:
obtaining a low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices;
copying data from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower low-power state current/power consumption than the first set of volatile memory devices; and
placing the first set of volatile memory devices into a power-down state to reduce power consumption.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
determining when to switch the first set of volatile memory devices into the power-down state after a period of inactivity.

### Claim 17 (depends on 15)

The method of claim 15, wherein the low-power state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
placing the second set of volatile memory devices into a power conservation state to reduce power consumption.

### Claim 19 (depends on 18)

The method of claim 18, wherein the power conservation state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

### Claim 20 (depends on 15)

The method of claim 15, wherein the low power state current/power consumption includes leakage current/power consumption and dynamic power consumption.

### Claim 21 (depends on 15)

The method of claim 15, further comprising:
compensating for temperature variations between the memory devices; and
normalizing the low-power state current/power consumption for each of the plurality of volatile memory devices based on their corresponding temperatures.

### Claim 22 (depends on 15)

The method of claim 15, wherein the first set of the volatile memory devices and the second set of the volatile memory devices are coupled to the same memory bus channel.

### Claim 23 (depends on 15)

The method of claim 15, further comprising:
obtaining a low-power state current/power consumption for each memory bank within each of the plurality of volatile memory devices;
copying data from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower low-power state current/power consumption than the first set of memory banks; and
placing the first set of memory banks into a power-down state.

### Claim 24

An electronic device, comprising:
means for obtaining a low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices;
means for copying data from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower low-power state current/power consumption than the first set of volatile memory devices; and
means for placing the first set of volatile memory devices into a power-down state to reduce power consumption.

### Claim 25 (depends on 24)

The device of claim 24, further comprising:
means for determining when to switch the first set of volatile memory devices into the power-down state after a period of inactivity.

### Claim 26 (depends on 24)

The device of claim 24, wherein the low-power state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

### Claim 27 (depends on 1)

The device of claim 1, wherein the processing circuit is further configured to:
means for placing the second set of volatile memory devices into a power conservation state to reduce power consumption.

### Claim 28 (depends on 27)

The device of claim 27, wherein the power conservation state maintains data in the second set of volatile memory devices, while the power-down state causes data in the first set of volatile memory devices to be lost.

### Claim 29 (depends on 24)

The device of claim 24, further comprising:
means for compensating for temperature variations between the memory devices; and
means for normalizing the low-power state current/power consumption for each of the plurality of volatile memory devices based on their corresponding temperatures.

### Claim 30 (depends on 24)

The device of claim 24, further comprising:
means for obtaining a low-power state current/power consumption for each memory bank within each of the plurality of volatile memory devices;
means for copying data from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower low-power state current/power consumption than the first set of memory banks; and
means for placing the first set of memory banks into a power-down state.

### Claim 31

A processor-readable storage medium having instructions stored thereon, which when executed by at least one processor causes the at least one processor to:
obtain a low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices;
copy data from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower low-power state current/power consumption than the first set of volatile memory devices; and
place the first set of volatile memory devices into a power-down state to reduce power consumption.

### Claim 32 (depends on 31)

The machine-readable storage medium of claim 31, which when executed by the at least one processor further causes the at least one processor to:
compensate for temperature variations between the memory devices; and
normalize the low-power state current/power consumption for each of the plurality of volatile memory devices based on their corresponding temperatures.

### Claim 33 (depends on 31)

The machine-readable storage medium of claim 31, which when executed by the at least one processor further causes the at least one processor to:
obtain a low-power state current/power consumption for each memory bank within each of the plurality of volatile memory devices;
copy data from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower low-power state current/power consumption than the first set of memory banks; and
place the first set of memory banks into a power-down state.