# US 2014/0195835 A1 · System and method for providing power savings in a processor environment

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- Number: US 2014/0195835 A1
- Document ID: US20140195835A1
- Status: Published application
- Kind: A1
- Application number: 13/734,577
- Filed: 2013-01-04
- Published: 2014-07-10
- Earliest claimed: 2013-01-04
- Assignees: Intel Corporation
- Inventors: Sun Zheng E.; Ting Lok Song; Poh Thiam Teoh; Jennifer Chin; Say Cheong Gan; Sujea Lim; Su Wei Lim
- Web page: https://patentgrep.com/patent/US20140195835A1

## CPC

- G06F 1/3253: {Power saving in bus}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

## Claims

### Claim 1

A method for reducing power consumption in a processing environment, comprising:
powering down a root port;
initiating a first downstream cycle by a central processing unit (CPU) to the root port;
identifying a power up activity for the CPU; and
triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port.

### Claim 2 (depends on 1)

The method of claim 1, wherein the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion.

### Claim 3 (depends on 1)

The method of claim 1, wherein a prewake indicator is sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

### Claim 4 (depends on 1)

The method of claim 1, wherein the root port is associated with a Peripheral Component Interconnect Express (PCIe) port.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
receiving the second downstream cycle; and
sending the second downstream cycle to a device.

### Claim 6 (depends on 1)

The method of claim 1, wherein the CPU is coupled to a plurality of high-speed serial input/output (I/O) ports.

### Claim 7 (depends on 1)

The method of claim 1, wherein the power state is associated with a PCIe root port Idle Power state.

### Claim 8

An apparatus for reducing power consumption in a processing environment, comprising:
a central processing unit (CPU); and
a root port configured to be powering down, wherein the CPU is configured to initiate a first downstream cycle to the root port and to receive a power up indicator, and wherein an exit flow is to be triggered for a power state in conjunction with sending a second downstream cycle to the root port.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein a prewake indicator is sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

### Claim 11 (depends on 8)

The apparatus of claim 8, wherein the root port is associated with a Peripheral Component Interconnect Express (PCIe) port.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the second downstream cycle is sent to a device.

### Claim 13 (depends on 8)

The apparatus of claim 8, wherein the CPU is coupled to a plurality of high-speed serial input/output (I/O) ports.

### Claim 14

A method for reducing power consumption in a processing environment, comprising:
identifying a power management state associated with a central processing unit (CPU);
applying a power down state through a common mode turn off;
applying a transmit (Tx) common mode disable pin to a physical layer (PHY) in order to change a power state level associated with the CPU.

### Claim 15 (depends on 14)

The method of claim 14, wherein the common mode disable pin is de-asserted to enable the Tx common mode.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
receiving a status signal at an input/output (I/O) controller to indicate a power state level.

### Claim 17 (depends on 14)

The method of claim 14, wherein the power management state is a selected one of a group of states, the group consisting of:
a) a link disable state;
b) a runtime state;
c) a detect state; and
d) an unconfigured lanes state.

### Claim 18 (depends on 14)

The method of claim 14, wherein the Tx common mode is not turned off until a signal is received.

### Claim 19 (depends on 14)

The method of claim 14, wherein the PHY allows a root port to exit to a power state level by returning a status signal.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
sampling the pin in order to determine when to turn off the Tx common mode.

### Claim 21

An apparatus for reducing power consumption in a processing environment, comprising:
a central processing unit (CPU); and
a root port coupled to the CPU, wherein a power management state associated with a central processing unit (CPU) is identified, and wherein a power down state is applied through a common mode turn off, and wherein a transmit (Tx) common mode disable pin is applied to a physical layer (PHY) in order to change a power state level associated with the CPU.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein the common mode disable pin is de-asserted to enable the Tx common mode.

### Claim 23 (depends on 21)

The apparatus of claim 21, wherein the power management state is a selected one of a group of states, the group consisting of:
a) a link disable state;
b) a runtime state;
c) a detect state; and
d) an unconfigured lanes state.

### Claim 24 (depends on 21)

The apparatus of claim 21, wherein the PHY allows the root port to exit to a power state level by returning a status signal.

### Claim 25 (depends on 21)

The apparatus of claim 21, wherein the pin is sampled in order to determine when to turn off the Tx common mode.