# US 2014/0195833 A1 · Adaptive low-power link-state entry policy for active interconnect link power management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195833 A1 - Document ID: US20140195833A1 - Status: Published application - Kind: A1 - Application number: 13/994,786 - Filed: 2012-04-24 - Published: 2014-07-10 - Earliest claimed: 2012-04-24 - Assignees: Intel Corporation - Inventors: Ren Wang; Ahmad Samih; Christian Maciocco; Tsung-Yuan Charlie Tai; James Jimbo Alexander; Prashant R. Chandra - Web page: https://patentgrep.com/patent/US20140195833A1 ## CPC - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 1/3253: {Power saving in bus} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Methods and apparatus for implementing active interconnect link power management using an adaptive low-power link-state entry policy. The power state of an interconnect link or fabric is changed in response to applicable conditions determined by low-power link-state entry policy logic in view of runtime traffic on the interconnect link or fabric. The low-power link-state policy logic may be configured to include consideration of operating system input and Quality of Service (QoS) requirements for applications and devices employing the link or fabric, and device latency tolerance requirements. ## Claims ### Claim 1 A method comprising: implementing an adaptable low-power link-state policy for an interconnect link; monitoring traffic on the interconnect link to produce dynamic traffic data; adjusting the adaptable low-power link-state entry policy for the interconnect link in response to the dynamic traffic data. ### Claim 2 (depends on 1) The method of claim 1, further comprising: receiving operating system configuration information; and employing the operating system configuration information in implementing the adaptable low-power link-state policy for the interconnect link. ### Claim 3 (depends on 1) The method of claim 1, further comprising: receiving application Quality of Service (QoS) requirements for an application that at least one of transmits or receives data using the interconnect link; and employing the application QOS requirements in implementing the adaptable low-power link-state policy for the interconnect link. ### Claim 4 (depends on 1) The method of claim 1, further comprising: receiving device Quality of Service (QoS) requirements for a device coupled to the interconnect link; and employing the device QOS requirements in implementing the adaptable low-power link-state policy for the interconnect link. ### Claim 5 (depends on 1) The method of claim 1, further comprising: receiving device latency tolerance requirements for a device coupled to the interconnect link; and employing the device latency tolerance requirements in implementing the adaptable low-power link-state policy for the interconnect link. ### Claim 6 (depends on 1) The method of claim 1, wherein the link comprises a PCI Express link. ### Claim 7 (depends on 1) The method of claim 1, wherein the interconnect link comprises one of a QuickPath Interconnect (QPI) link, an IOSF (Intel on-chip System Fabric) link or a Thunderbolt link. ### Claim 8 (depends on 1) The method of claim 1, wherein the adaptable low-power link-state policy is implemented by adapting an Active Status Power Management (ASPM) link timeout policy in response to the traffic data. ### Claim 9 (depends on 1) The method of claim 1, further comprising: determining a performance level of the adaptable low-power link-state policy; and adjusting parameters in logic for implementing the adaptable low-power link-state policy. ### Claim 10 An apparatus comprising: an interconnect link, coupled between an upstream port and a downstream port; a traffic monitor, configured to generate traffic data when the apparatus is operating; and an adaptable low-power link-state policy block, configured to receive traffic data from the traffic monitor and to dynamically adjust a low-power link-state policy for the interconnect link in response to the traffic data. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the adaptable low-power link-state policy block is configured to receive configuration input from an operating system and employ the configuration information in implementing the low-power link-state policy for the interconnect link. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the adaptable low-power link-state policy block is configured to receive application Quality of Service (QoS) requirements for at least one application and employ the application QoS requirements in implementing the low-power link-state policy for the interconnect link. ### Claim 13 (depends on 10) The apparatus of claim 10, wherein the adaptable low-power link-state policy block is configured to receive device Quality of Service (QoS) requirements for a device associated with the interconnect link and to employ the device QoS requirements in implementing the low-power link-state policy for the interconnect link. ### Claim 14 (depends on 10) The apparatus of claim 10, wherein the adaptable low-power link-state policy block is configured to receive device latency tolerance requirements for a device associated with the interconnect link and to employ the device latency tolerance requirements in implementing the low-power link-state policy for the interconnect link. ### Claim 15 (depends on 10) The apparatus of claim 10, wherein the interconnect link comprises a PCI Express link. ### Claim 16 A processor, comprising: a plurality of processor cores; a first interconnect interface, including a first port configured to send and receive communication traffic over a first interconnect link employing the first port at one end of the interconnect link; and a traffic monitor, configured to generate traffic data corresponding to traffic detected at the first port when the apparatus is operating, wherein the first port includes an adaptable low-power link-state policy block, configured to receive traffic data from the traffic monitor and to dynamically adjust a low-power link-state policy for the first interconnect link in response to the traffic data. ### Claim 17 (depends on 16) The processor of claim 16, wherein the adaptable low-power link-state policy block is configured to receive configuration input from an operating system and employ the configuration information in implementing the low-power link-state policy for the first interconnect link. ### Claim 18 (depends on 16) The processor of claim 16, wherein the adaptable low-power link-state policy block is configured to receive application Quality of Service (QoS) requirements for at least one application and employ the application QoS requirements in implementing the low-power link-state policy for the first interconnect link. ### Claim 19 (depends on 16) The processor of claim 16, wherein the adaptable low-power link-state policy block is configured to receive device Quality of Service (QoS) requirements for a device associated with the first interconnect link and to employ the device QoS requirements in implementing the low-power link-state policy for the first interconnect link. ### Claim 20 (depends on 16) The processor of claim 16, wherein the adaptable low-power link-state policy block is configured to receive device latency tolerance requirements for a device associated with the first interconnect link and to employ the device latency tolerance requirements in implementing the low-power link-state policy for the first interconnect link.