# US 2014/0195832 A1 · Accelerated cache rinse when preparing a power state transition

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- Number: US 2014/0195832 A1
- Document ID: US20140195832A1
- Status: Published application
- Kind: A1
- Application number: 13/738,378
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Paul E. Kitchin; William L. Walker
- Web page: https://patentgrep.com/patent/US20140195832A1

## CPC

- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods, integrated circuit devices, and fabrication processes relating to power management transitions of a compute unit comprising a cache are presented. One method includes, responsive to an indication that the compute unit is attempting to enter a low power state, detecting at least one line of the cache differing from the corresponding line in memory, writing differing data from the at least one differing line to the memory, flushing at least one remaining differing line of the cache, and permitting the compute unit to enter the low power state, wherein the detecting and the writing are performed at a first frequency prior to the indication and at a second frequency subsequent the indication, and the second frequency is higher than the first frequency.

## Claims

### Claim 1

A method, comprising:
detecting at least one line of a cache of a compute unit that differs from a corresponding line in a memory;
writing differing data from the at least one differing line of the cache to the memory; and
flushing at least one remaining line of the cache that differs from a corresponding line in the memory;
wherein the detecting and the writing are performed at a first frequency when the compute unit is in a high power state and at a second frequency in response to the compute unit attempting to enter a low power state; and the second frequency is higher than the first frequency.

### Claim 2 (depends on 1)

The method of claim 1, further comprising saving an architectural state of the compute unit to a memory, in response to the compute unit attempting to enter the low power state.

### Claim 3 (depends on 2)

The method of claim 2, wherein the detecting and the writing are performed at the second frequency prior to completion of the saving.

### Claim 4 (depends on 2)

The method of claim 2, wherein the memory is a main memory.

### Claim 5 (depends on 1)

The method of claim 1, further comprising handshaking between the compute unit and a power management unit in response to the compute unit attempting to enter a low power state.

### Claim 6 (depends on 1)

The method of claim 1, wherein the writing is performed without evicting the at least one differing line from the cache.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second frequency is a maximum frequency.

### Claim 8 (depends on 1)

The method of claim 1, wherein the at least one differing cache line is a modified cache line.

### Claim 9 (depends on 1)

The method of claim 1, wherein the at least one differing cache line is a dirty cache line.

### Claim 10

An apparatus, comprising:
a compute unit comprising a cache, wherein the compute unit is configured to indicate it is attempting to enter a low power state and flush at least one modified line of the cache subsequent the indication;
a power management unit configured to permit the compute unit to enter the low power state; and
a cache rinser configured to detect at least one line of the cache that differs from a corresponding line in a memory and write differing data from the at least one differing line to the memory, wherein the cache rinser is configured to detect and write at a first frequency prior to the indication by the compute unit and at a second frequency subsequent the indication, and the second frequency is higher than the first frequency.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the memory is configured to store at least an architectural state of the compute unit and at least one line of the cache.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the cache rinser is further configured to detect and write at the second frequency prior to completion of the storing of the architectural state.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the compute unit and the power management unit are further configured to handshake subsequent the indicating and prior to the storing of the architectural state.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the cache rinser is configured to write the differing data without evicting the at least one differing line from the cache.

### Claim 15 (depends on 10)

The apparatus of claim 10, wherein the second frequency is the maximum frequency of the cache rinser.

### Claim 16 (depends on 10)

The apparatus of claim 10, wherein the at least one differing cache line is a modified cache line.

### Claim 17 (depends on 10)

The apparatus of claim 10, wherein the at least one differing cache line is a dirty cache line.

### Claim 18

A non-transitory computer-readable medium storing instructions executable by at least one processor to fabricate an apparatus, the apparatus comprising:
a compute unit comprising a cache, wherein the compute unit is configured to indicate it is attempting to enter a low power state and flush at least one modified line of the cache subsequent the indication;
a power management unit configured to permit the compute unit to enter the low power state; and
a cache rinser configured to detect at least one line of the cache differing from a corresponding line in a memory and write differing data from the at least one differing line to the memory, wherein the cache rinser is configured to detect and write at a first frequency prior to the indication by the compute unit and at a second frequency subsequent the indication, wherein the second frequency is higher than the first frequency.

### Claim 19 (depends on 18)

The non-transitory computer readable storage medium of claim 18, wherein the compute unit and the power management unit are further configured to handshake subsequent the indicating.

### Claim 20 (depends on 18)

The non-transitory computer readable storage medium of claim 18, wherein the cache rinser is configured to write the differing data without evicting the at least one differing line from the cache.

### Claim 21 (depends on 18)

The non-transitory computer readable storage medium of claim 18, wherein the second frequency is the maximum frequency of the cache rinser.

### Claim 22 (depends on 18)

The non-transitory computer readable storage medium of claim 18, wherein the at least one differing cache line is a modified cache line.

### Claim 23 (depends on 18)

The non-transitory computer readable storage medium of claim 18, wherein the at least one differing cache line is a dirty cache line.