# US 2014/0195830 A1 · System and method for power management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195830 A1 - Document ID: US20140195830A1 - Status: Published application - Kind: A1 - Application number: 13/734,612 - Filed: 2013-01-04 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: Intel Corporation - Inventors: Jennifer Chin; Su Wei Lim; Poh Thiam Teoh; Ting Lok Song; Sun Zheng E; Say Cheong Gan; Sujea Lim; Ming Yi Lim - Web page: https://patentgrep.com/patent/US20140195830A1 ## CPC - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/1626: {with a single-body enclosure integrating a flat display, e.g. Personal Digital Assistants [PDAs]} - G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality - G06F 1/3218: of display devices - G06F 1/3243: {Power saving in microcontroller unit} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 2213/0026: PCI express - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device. ## Claims ### Claim 1 A system, comprising: a processor; and a memory to store instructions that when executed by the processor performs operations, comprising: evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the plurality of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device. ### Claim 2 (depends on 1) The system of claim 1, wherein the pin is associated with a clock request (CLKREQ) pin. ### Claim 3 (depends on 2) The system of claim 2, wherein the clock request pin is used to detect a hot plug event in order to power up the PHY. ### Claim 4 (depends on 1) The system of claim 1, wherein the electronic device is a mobile computing device configured to be docked at a docking station. ### Claim 5 (depends on 1) The system of claim 1, wherein a docking interconnect is provided for the electronic device. ### Claim 6 (depends on 1) The system of claim 1, wherein the plurality of ports are Peripheral Component Interconnect Express (PCIe) ports. ### Claim 7 (depends on 1) The system of claim 1, wherein the plurality of ports are unpopulated and configured for performing the disabling of the squelch function. ### Claim 8 (depends on 1) The system of claim 1, wherein a root port of the plurality of ports provides power to the PHY in response to the electronic device being docked. ### Claim 9 (depends on 1) The system of claim 1, wherein a root port of the plurality of ports provides power to the PHY in response to the electronic device being connected to an external monitor. ### Claim 10 A system, comprising: a processor; and a memory to store instructions that when executed by the processor performs operations, comprising: identifying a power management event (PME) timeout; directing a receiver in a physical layer (PHY) to turn off; transitioning from a powered-on link state to a recovery state; and resuming a detection state associated with a predetermined timeout associated with failing to receive a sequence from the electronic device. ### Claim 11 (depends on 10) The system of claim 10, wherein incoming data is cut off from the electronic device in response to the PHY being turned off. ### Claim 12 (depends on 10) The system of claim 10, wherein the detection state is resumed before indicating a layer 2/layer 3 (L2/L3) ready state for the electronic device. ### Claim 13 (depends on 10) The system of claim 10, wherein the detection state is resumed before clearing a runtime-entry configuration bit for the electronic device. ### Claim 14 (depends on 10) The system of claim 10, wherein a runtime element is used to enable the PHY to be power gated. ### Claim 15 (depends on 10) The system of claim 10, wherein a receiver termination remains enabled and a transmitter common mode is turned off as the PHY is power gated. ### Claim 16 (depends on 10) The system of claim 10, wherein power is to be removed from the electronic device such that the electronic device resides in a device power state and a root port remains in a system working state. ### Claim 17 A system, comprising: a processor; and a memory to store instructions that when executed by the processor performs operations, comprising: providing a configuration bit of a root port; initiating a power management event turn off/acknowledgment handshake signal for the root port for putting a corresponding link into layer 2/layer 3 (L2/L3) ready state; instructing a power management controller (PMC) to assert a reset for the electronic device; and removing power such that the electronic device transitions to a cold state. ### Claim 18 (depends on 17) The system of claim 17, wherein the corresponding link is put into L2/L3 ready state independent of other ports associated with the electronic device. ### Claim 19 (depends on 17) The system of claim 17, wherein the configuration bit is set by software to initiate a turn off handshake signal. ### Claim 20 (depends on 17) The system of claim 17, further comprising: initiating an exit for the electronic device from a runtime mechanism by asserting a wake signal. ### Claim 21 (depends on 20) The system of claim 20, wherein assertion of the wake signal causes the PMC to generate a signal for restoring power to the electronic device and for sequencing the electronic device out of a reset state. ### Claim 22 (depends on 17) The system of claim 17, wherein the configuration bit is cleared on entry into the L2/L3 ready state. ### Claim 23 (depends on 17) The system of claim 17, wherein as part of an exit operation, another configuration bit is set to move the root port from an L2/L3 ready state to a detect state. ### Claim 24 (depends on 17) The system of claim 17, wherein while the electronic device is in a cold state after a successful runtime entry, a runtime exit configuration bit is programmed. ### Claim 25 An apparatus to manage power for at least one processor, comprising: logic, the logic at least partially including hardware logic, to: evaluate a plurality of ports associated with an electronic device; determine that a particular pin associated with at least one of the plurality of the ports is not receiving a signal; disable a squelch function associated with the electronic device; and gate power associated with a physical layer (PHY) of the electronic device. ### Claim 26 (depends on 25) The apparatus of claim 25, wherein the pin is associated with a clock request (CLKREQ) pin. ### Claim 27 (depends on 26) The apparatus of claim 26, wherein the clock request pin is used to detect a hot plug event in order to power up the PHY. ### Claim 28 (depends on 25) The apparatus of claim 25, wherein the electronic device is a mobile computing device configured to be docked at a docking station. ### Claim 29 (depends on 25) The apparatus of claim 25, wherein a docking interconnect is provided for the electronic device. ### Claim 30 (depends on 25) The apparatus of claim 25, wherein the plurality of ports are Peripheral Component Interconnect Express (PCIe) ports.