# US 2014/0195828 A1 · Dynamically measuring power consumption in a processor

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- Number: US 2014/0195828 A1
- Document ID: US20140195828A1
- Status: Published application
- Kind: A1
- Application number: 13/996,266
- Filed: 2012-03-30
- Published: 2014-07-10
- Earliest claimed: 2012-03-30
- Assignees: Intel Corporation
- Inventors: Ankush Varma; Krishnakanth V. Sistla; Martin T. Rowland; Vivek Garg; James S. Burns
- Web page: https://patentgrep.com/patent/US20140195828A1

## CPC

- G01R 21/133: by using digital technique
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/324: by lowering clock frequency
- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 1/3296: by lowering the supply or operating voltage
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.

## Claims

### Claim 1

A processor comprising:
a plurality of cores to independently execute instructions;
a first sensor to measure a first power consumption level of the processor based at least in part on a plurality of events occurring on the plurality of cores; and
a hybrid logic to combine the first power consumption level and a second power consumption level of the processor determined based on a dynamic current provided to the processor.

### Claim 2 (depends on 1)

The processor of claim 1, further comprising a power controller to control at least one of an operating frequency and a voltage of the processor based on the combined first and second power consumption levels and a power limit of the processor.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the power controller is to use the first power consumption level to control the at least one of the operating frequency and the voltage if the first power consumption level is less than a threshold, and otherwise use the second power consumption level to control the at least one of the operating frequency and the voltage.

### Claim 4 (depends on 1)

The processor of claim 1,, wherein the first sensor comprises a logic to receive counter information from a plurality of event counters associated with each of the plurality of cores and to measure the first power consumption level based on the counter information.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the hybrid logic is to combine the first power consumption level and the second power consumption level by:
generation of a first correction factor using the first power consumption level and the second power consumption level; and
generation of a second correction factor using the second power consumption level and the first correction factor.

### Claim 6 (depends on 5)

The processor of claim 5, wherein the hybrid logic is to determine the hybrid power consumption level using the second power consumption level and the first and second correction factors.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the hybrid logic is to execute a low power load on the processor and calculate the first and second power consumption levels using sensor information from the first sensor and the dynamic current, respectively, and determine and store an offset based on the first and second power consumption levels.

### Claim 8 (depends on 7)

The processor of claim 7, wherein the hybrid logic is to execute a high power load on the processor and calculate the second power consumption level using the dynamic current, and determine and store a slope based on the offset and the second power consumption level.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the hybrid logic is to receive the dynamic current and calculate the second power consumption level using the dynamic current, and determine the hybrid power consumption level using second power consumption level, the slope and the offset.

### Claim 10

A method comprising:
receiving, in a first logic of a processor, sensor information from a digital power meter of the processor, and calculating a first power consumption level of the processor using the sensor information from the digital power meter;
receiving, in the first logic, sensor information from a current sensor configured to measure a current delivered by a voltage regulator coupled to the processor, and calculating a second power consumption level of the processor using the sensor information from the current sensor; and
combining, in the first logic, the first and second power consumption levels to obtain a hybrid power consumption level of the processor.

### Claim 11 (depends on 10)

The method of claim 10, further comprising controlling at least one of an operating frequency and a voltage of the processor based on the hybrid power consumption level and a power limit of the processor.

### Claim 12 (depends on 11)

The method of claim 11, wherein combining the first and second power consumption levels comprises:
if the first power consumption level is less than a threshold, using the first power consumption level to control the at least one of the operating frequency and the voltage; and
otherwise, using the second power consumption level to control the at least one of the operating frequency and the voltage.

### Claim 13 (depends on 11)

The method of claim 11, wherein combining the first and second power consumption levels comprises:
generating a first correction factor using the first power consumption level and the second power consumption level; and
generating a second correction factor using the second power consumption level and the first correction factor.

### Claim 14 (depends on 13)

The method of claim 13, further comprising determining the hybrid power consumption level using the second power consumption level and the first and second correction factors.

### Claim 15 (depends on 14)

The method of claim 14, further comprising controlling at least one of an operating frequency and a voltage of the processor based on the hybrid power consumption level.

### Claim 16

A system comprising:
a multicore processor including a plurality of cores to independently execute instructions, each of the plurality of cores including at least one event counter to count events occurring on the core, a digital power meter to calculate a first power consumption level based on information from the event counters, a second power meter to calculate a second power consumption level based on a current delivered to the multicore processor from a voltage regulator, and a power controller including a first logic to generate a combined power consumption level of the multicore processor using the first and second power consumption levels;
the voltage regulator coupled to the multicore processor to provide a regulated voltage to the multicore processor; and
a dynamic random access memory (DRAM) coupled to the multicore processor.

### Claim 17 (depends on 16)

The system of claim 16, wherein the first logic is to:
cause a low power load level to occur on the multicore processor and calculation of the first and second power consumption levels during the low power load level; and
determine and store an offset based on first and second power consumption levels.

### Claim 18 (depends on 17)

The system of claim 17, wherein the first logic is to:
cause a high power load level to occur on the multicore processor and calculation of the second power consumption level during the high power load level; and
determine and store a slope based on the offset and the second power consumption level.

### Claim 19 (depends on 18)

The system of claim 18, wherein the first logic is to receive the second power consumption level during normal operation of the system and determine the hybrid power consumption level using the second power consumption level, the slope and the offset.

### Claim at position 20

20-23. (canceled)

### Claim 24

A processor comprising:
a plurality of execution units each to independently execute instructions;
a first sensor to measure a first power consumption level of the processor based at least in part on a plurality of events occurring on the plurality of execution units; and
a logic to combine the first power consumption level and a second power consumption level of the processor determined based on a dynamic current provided to the processor.

### Claim 25 (depends on 24)

The processor means of claim 24, further comprising a controller to control at least one of an operating frequency and a voltage of the processor means based on the combined first and second power consumption levels and a power limit of the processor.

### Claim 26 (depends on 24)

The processor means of claim 24, further comprising a regulator to provide a regulated voltage to the processor, the regulator to further provide a level of the dynamic current provided to the processor.