# US 2014/0195787 A1 · Tracking speculative execution of instructions for a register renaming data store > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195787 A1 - Document ID: US20140195787A1 - Status: Published application - Kind: A1 - Application number: 13/737,153 - Filed: 2013-01-09 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Luca SCALABRINO; Melanie Emanuelle Lucie TEYSSIER; Cedric Denis Robert AIRAUD; Guillaume SCHON - Web page: https://patentgrep.com/patent/US20140195787A1 ## CPC - G06F 9/3842: {Speculative instruction execution} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/384: {Register renaming} - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations. ## Claims ### Claim 1 A data processing apparatus for processing a stream of program instructions, comprising first processing circuitry configured to process at least some of the program instructions, the first processing circuitry comprising: a plurality of registers for storing data; register renaming circuitry configured to map architectural register specifiers identified by the program instructions to physical register specifiers identifying the plurality of registers; and a renaming data store configured to store a plurality of renaming entries, each renaming entry for identifying a register mapping between at least one of the architectural register specifiers and at least one of the physical register specifiers; wherein: at least some renaming entries have a corresponding count value, the count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value; a speculation point comprising a point of program flow of the stream of program instructions following which at least one program instruction is executed speculatively by the data processing apparatus before it is known whether the at least one program instruction should have been executed following the speculation point; and the count value comprises an N-bit value, where N is an integer and N>1. ### Claim 2 (depends on 1) The data processing apparatus according to claim 1, wherein the first processing circuitry is configured to process a predetermined class of program instructions from the stream of program instructions; and the second processing circuitry is configured to process other program instructions from the stream of program instructions. ### Claim 3 (depends on 2) The data processing apparatus according to claim 2, wherein the predetermined class of program instructions comprises program instructions for performing floating-point operations. ### Claim 4 (depends on 2) The data processing apparatus according to claim 2, wherein the predetermined class of program instructions comprises program instructions for performing single-instruction-multiple-data (SIMD) operations. ### Claim 5 (depends on 1) The data processing apparatus according to claim 1, wherein at least one renaming entry identifies: (a) a first register mapping to be used for the speculative execution of one of the at least one program instruction following a speculation point; and (b) a second register mapping for restoring previous register state if the at least one program instruction should not have been executed following the speculation point. ### Claim 6 (depends on 1) The data processing apparatus according to claim 1, wherein the speculation points include a plurality of types of speculation points. ### Claim 7 (depends on 6) The data processing apparatus according to claim 6, wherein the plurality of types of speculation points include at least one of branch operations and load/store operations. ### Claim 8 (depends on 6) The data processing apparatus according to claim 6, wherein the at least some renaming entries have a corresponding first count value indicating the number of unresolved speculation points of a first type occurring between generation of a previous first count value and generation of the first count value, and a corresponding second count value indicating the number of unresolved speculation points of a second type occurring between generation of a previous second count value and generation of the second count value. ### Claim 9 (depends on 1) The data processing apparatus according to claim 1, wherein the count value indicates a number of unresolved speculation points occurring between generation of the previous count value and generation of the count value, an unresolved speculation point comprising a speculation point for which, when generating the count value, it is unknown whether the at least one program instruction should have been executed following the speculation point. ### Claim 10 (depends on 1) The data processing apparatus according to claim 1, comprising monitoring circuitry configured to generate a speculation point count indicating the number of speculation points detected in the stream of program instructions; wherein the first processing circuitry comprises count value generating circuitry configured to generate the count value for a new renaming entry in dependence on the speculation point count generated by the monitoring circuitry. ### Claim 11 (depends on 10) The data processing apparatus according to claim 10, wherein: after generating the count value, the count value generating circuitry is configured to store the generated count value as a reference count value; and the count value generating circuitry is configured to generate a following count value by calculating a difference between the speculation point count generated by the monitoring circuitry and the reference count value. ### Claim 12 (depends on 11) The data processing apparatus according to claim 11, wherein the monitoring circuitry is configured to monitor whether the detected speculation points are resolved, wherein a speculation point is resolved when it is known whether the at least one program instruction should have been executed following the speculation point; the speculation point count generated by the monitoring circuitry indicates the number of unresolved speculation points detected in the stream of program instructions; and the count value generating circuitry is configured to decrement the reference count value in response to resolution of a speculation point. ### Claim 13 (depends on 1) The data processing apparatus according to claim 1, wherein the first processing circuitry comprises eviction control circuitry configured to control eviction of renaming entries from the renaming data store in dependence upon the count values corresponding to the at least some renaming entries. ### Claim 14 (depends on 8) The data processing apparatus according to claim 8, wherein the first processing circuitry comprises eviction control circuitry configured to control eviction of renaming entries from the renaming data store; wherein the eviction control circuitry is configured to perform a first eviction determination for determining whether a renaming entry of the at least some renaming entries can be evicted based on the first event count values, and to perform a second eviction determination for determining whether the renaming entry can be evicted based on the second event count values; and the eviction control circuitry is configured to allow the renaming entry to be evicted if both the first eviction determination and the second eviction determination determine that the oldest renaming entry can be evicted. ### Claim 15 (depends on 13) The data processing apparatus according to claim 13, wherein the eviction control circuitry comprises a resolution counter configured to generate a resolution count value indicating the number of resolved speculation points for which it is known whether the at least one program instruction should have been executed following the speculation point. ### Claim 16 (depends on 15) The data processing apparatus according to claim 15, wherein the eviction control circuitry is configured to perform an eviction determination for determining whether the oldest renaming entry of the at least some renaming entries can be evicted from the renaming data store; and if the count value for the oldest renaming entry indicates a number of speculation points which is less than the number of resolved speculation points indicated by the resolution count value, then the eviction determination determines that the oldest renaming entry can be evicted. ### Claim 17 (depends on 16) The data processing apparatus according to claim 16, wherein the eviction control circuitry is configured to perform a further eviction determination for determining whether at least one next oldest renaming entry of the at least some renaming entries can be evicted; and if the total of the numbers of speculation points indicated by the count values for the oldest renaming entry and the at least one next oldest renaming entry is less than the number of resolved speculation points indicated by the resolution count value, then the further eviction determination determines that the at least one next oldest renaming entry can be evicted. ### Claim 18 (depends on 17) The data processing apparatus according to claim 17, wherein the at least one next oldest renaming entry comprises a maximum of N next oldest renaming entries, where N is an integer. ### Claim 19 (depends on 1) The data processing apparatus according to claim 1, comprising power control circuitry configured to place the renaming data store in a power saving state if there are no valid renaming entries in the renaming data store. ### Claim 20 (depends on 10) The data processing apparatus according to claim 10, comprising power control circuitry configured to place at least the count value generating circuitry in a power saving state if there are no valid renaming entries in the renaming data store. ### Claim 21 (depends on 13) The data processing apparatus according to claim 13, comprising power control circuitry configured to place the eviction control circuitry in a power saving state if there are no valid renaming entries in the renaming data store ### Claim 22 A data processing apparatus for processing a stream of program instructions, comprising first processing means for processing at least some of the program instructions, the first processing means comprising: a plurality of register means for storing data; register renaming means for mapping architectural register specifiers identified by the program instructions to physical register specifiers identifying the plurality of register means; and renaming data storage means for storing a plurality of renaming entries, each renaming entry for identifying a register mapping between at least one of the architectural register specifiers and at least one of the physical register specifiers; wherein: at least some renaming entries have a corresponding count value, the count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value; a speculation point comprising a point of program flow of the stream of program instructions following which at least one program instruction is executed speculatively by the data processing apparatus before it is known whether the at least one program instruction should have been executed following the speculation point; and the count value comprises an N-bit value, where N is an integer and N>1. ### Claim 23 A data processing method for processing a stream of program instructions using a data processing apparatus comprising first processing circuitry configured to process at least some of the program instructions, the first processing circuitry comprising a plurality of registers for storing data; the method comprising: mapping architectural register specifiers identified by the program instructions to physical register specifiers identifying the plurality of registers; and storing a plurality of renaming entries in a renaming data store, each renaming entry for identifying a register mapping between at least one of the architectural register specifiers and at least one of the physical register specifiers; wherein: at least some renaming entries have a corresponding count value, the count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value; a speculation point comprising a point of program flow of the stream of program instructions following which at least one program instruction is executed speculatively by the data processing apparatus before it is known whether the at least one program instruction should have been executed following the speculation point; and the count value comprises an N-bit value, where N is an integer and N>1. ### Claim 24 A data processing apparatus for processing a stream of program instructions, comprising first processing circuitry configured to process at least some of the program instructions, the first processing circuitry comprising: a plurality of registers for storing data; register renaming circuitry configured to map architectural register specifiers identified by the program instructions to physical register specifiers identifying the plurality of registers; and a renaming data store configured to store a plurality of renaming entries, each renaming entry for identifying a register mapping between at least one of the architectural register specifiers and at least one of the physical register specifiers; wherein: at least some renaming entries have a corresponding count value, the count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value, the speculation points comprising branch operations or load/store operations; and the count value comprises an N-bit value, where N is an integer and N>1.