# US 2014/0195784 A1 · Method, device and system for controlling execution of an instruction sequence in a data stream accelerator

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- Number: US 2014/0195784 A1
- Document ID: US20140195784A1
- Status: Published application
- Kind: A1
- Application number: 13/993,850
- Filed: 2011-12-29
- Published: 2014-07-10
- Earliest claimed: 2011-12-29
- Assignees: Intel Corporation
- Inventors: Vladimir Ivanov
- Web page: https://patentgrep.com/patent/US20140195784A1

## CPC

- G06F 9/3885: {using a plurality of independent parallel functional units}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 15/82: data or demand driven
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Techniques and mechanisms for controlling execution of an instruction sequence in a data stream processing engine. In an embodiment, a control unit of the data stream processing engine detects that execution of a first instruction in an instruction sequence has ended. In another embodiment, the control unit determines information regarding a next instruction of the instruction sequence which is to be executed. Control signals may be sent from the control unit to form a data path set for execution of the next instruction in the instruction sequence.

## Claims

### Claim 1

An integrated circuit for operation in a data stream processing engine (DSPE) of an accelerator, the integrated circuit comprising:
an instruction sequencer to detect a first control signal sent from a data path module of the DSPE to the integrated circuit, the first control signal indicating that the data path module has completed an execution of a first instruction in a sequence of instructions for a data processing task, the first instruction to perform multiple atomic operations; and
a control signal generator coupled to receive instruction information sent from the instruction sequencer in response to the first control signal, the instruction information indicating that a second instruction is a next instruction in the sequence of instructions to be executed, the second instruction to perform multiple atomic operations, the control signal generator to send to the data path module a plurality of control signals based on the instruction information, the plurality of control signals for multiple data processing units (DPUs) of the data path module to form a set of one or more data paths corresponding to the second instruction.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of control signals are based on a bit field corresponding to the second instruction, wherein each bit in the bit field represents a configuration of a respective data processing unit (DPU) of the multiple DPUs.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of control signals includes signals sent in parallel to different respective ones of the multiple DPUs.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the first control signal specifies a status of a write port of the data path module.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, further comprising:
a status collector to receive a status signal generated during the execution of the first instruction, the instruction sequencer further to determine, based on the status signal, that the second instruction is the next instruction in the sequence of instructions to be executed.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the set of one or more data paths are formed for a data driven execution of the second instruction.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, further comprising a task description decoder to receive from a microcontroller of the accelerator a descriptor of the data processing task, the instruction sequencer further to configure the data path module for data driven execution of the first instruction in response to the received descriptor of the data processing task.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, the task description decoder further to signal a local load store unit of the DSPE to load data for the data processing task, wherein the task description decoder to signal the local load store unit in response to the received descriptor of the data processing task.

### Claim 9

A method at a control unit in a data stream processing engine (DSPE) of an accelerator, the method comprising:
detecting a first control signal sent from a data path module of the DSPE, the first control signal indicating that the data path module has completed an execution of a first instruction in a sequence of instructions for a data processing task, the first instruction to perform multiple atomic operations;
in response to the first control signal, providing instruction information indicating that a second instruction is a next instruction in the sequence of instructions to be executed, the second instruction to perform multiple atomic operations;
sending to the data path module a plurality of control signals based on the instruction information, the plurality of control signals for multiple data processing units (DPUs) of the data path module to form a set of one or more data paths corresponding to the second instruction.

### Claim 10 (depends on 9)

The method of claim 9, wherein the plurality of control signals are based on a bit field corresponding to the second instruction, wherein each bit in the bit field represents a configuration of a respective data processing unit (DPU) of the multiple DPUs.

### Claim 11 (depends on 9)

The method of claim 9, wherein the plurality of control signals includes signals sent in parallel to different respective ones of the multiple DPUs.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first control signal specifies a status of a port of the data path module.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
receiving a status signal generated during the execution of the first instruction, the instruction sequencer further to determine, based on the status signal, that the second instruction is the next instruction in the sequence of instructions to be executed.

### Claim 14 (depends on 9)

The method of claim 9, wherein the set of one or more data paths are formed for a data driven execution of the second instruction.

### Claim 15 (depends on 9)

The method of claim 9, further comprising:
receiving from a microcontroller of the accelerator a descriptor of the data processing task; and
configuring the data path module for data driven execution of the first instruction in response to the received descriptor of the data processing task.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
signaling a local load store unit of the DSPE to load data for the data processing task, the signaling the local load store unit in response to the received descriptor of the data processing task.

### Claim 17

A computer platform comprising:
a processor;
an accelerator coupled to the processor, the accelerator to perform a data processing task for the processor, the accelerator including:
a data path module including multiple data processing units (DPUs); and
a control unit including:
an instruction sequencer to detect a first control signal sent from the data path module, the first control signal indicating that the data path module has completed an execution of a first instruction in a sequence of instructions for the data processing task, the first instruction to perform multiple atomic operations; and
a control signal generator coupled to receive instruction information sent from the instruction sequencer in response to the first control signal, the instruction information indicating that a second instruction is a next instruction in the sequence of instructions to be executed, the second instruction to perform multiple atomic operations, the control signal generator to send to the data path module a plurality of control signals based on the instruction information, the plurality of control signals for the multiple DPUs to form a set of one or more data paths corresponding to the second instruction; and
a network interface coupled to the processor, the network interface to couple the computer platform to a network.

### Claim 18 (depends on 17)

The computer platform of claim 17, wherein the plurality of control signals are based on a bit field corresponding to the second instruction, wherein each bit in the bit field represents a configuration of a respective data processing unit (DPU) of the multiple DPUs.

### Claim 19 (depends on 17)

The computer platform of claim 17, wherein the plurality of control signals includes signals sent in parallel to different respective ones of the multiple DPUs.

### Claim 20 (depends on 17)

The computer platform of claim 17, wherein the first control signal specifies a status of a write port of the data path module.

### Claim 21 (depends on 17)

The computer platform of claim 17, the accelerator further comprising:
a status collector to receive a status signal generated during the execution of the first instruction, the instruction sequencer further to determine, based on the status signal, that the second instruction is the next instruction in the sequence of instructions to be executed.

### Claim 22 (depends on 17)

The computer platform of claim 17, wherein the set of one or more data paths are formed for a data driven execution of the second instruction.

### Claim 23 (depends on 17)

The computer platform of claim 17, the accelerator further comprising a task description decoder to receive from a microcontroller of the accelerator a descriptor of the data processing task, the instruction sequencer further to configure the data path module for data driven execution of the first instruction in response to the received descriptor of the data processing task.

### Claim 24 (depends on 23)

The computer platform of claim 23, the task description decoder further to signal a local load store unit of the DSPE to load data for the data processing task, wherein the task description decoder to signal the local load store unit in response to the received descriptor of the data processing task.