# US 2014/0195778 A1 · Instruction and logic to provide vector load-op/store-op with stride functionality > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195778 A1 - Document ID: US20140195778A1 - Status: Published application - Kind: A1 - Application number: 13/977,728 - Filed: 2011-09-26 - Published: 2014-07-10 - Earliest claimed: 2011-09-26 - Assignees: Intel Corporation - Inventors: Elmoustapha Ould-Ahmed-Vall; Kshitij A. Doshi; Suleyman Sair; Charles R. Yount - Web page: https://patentgrep.com/patent/US20140195778A1 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30018: {Bit or string instructions} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/3004: {to perform operations on memory} - G06F 9/30101: {Special purpose registers} - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode} - G06F 9/3455: {using stride} - G06F 9/3808: {for instruction reuse, e.g. trace cache, branch target cache} - G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/38873: {Iterative single instructions for multiple data lanes [SIMD]} - G06F 15/8061: {Details on data memory access} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults. ## Claims ### Claim 1 A processor comprising: a first register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the first register corresponds to a multiple of a stride length from a beginning address for a corresponding data element in a memory, wherein for each data field in the first register, a first value indicates the corresponding element has not yet been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory; a decode stage to decode a first instruction specifying the first register and a set of load operations corresponding to one or more of the first plurality of data fields and specifying a second single-instruction-multiple-data (SIMD) operation; and one or more execution units, responsive to the decoded first instruction, to: read the values of each of the data fields in the first register; for each data field of the plurality of data fields in the first register having the first value, to load the corresponding data element from the memory and to store the corresponding data element into a second register, the second register having a second plurality of data fields, a portion of which to store the loaded data elements, and to change the value of the corresponding data field in the first register from the first value to the second value; and to perform the second SIMD operation using the data elements stored in the portion of the second plurality of data fields to generate corresponding result data elements. ### Claim 2 (depends on 1) The processor of claim 1, wherein the first value is one. ### Claim 3 (depends on 1) The processor of claim 1, wherein the second value is zero. ### Claim 4 (depends on 1) The processor of claim 1, said one or more execution units, responsive to the decoded first instruction, to duplicate the plurality of data fields in the first register. ### Claim 5 (depends on 4) The processor of claim 4, said one or more execution units, responsive to the decoded first instruction, to duplicate each of the plurality of data fields having the first value in the first register when the value of that data field in the first register is changed from the first value to the second value. ### Claim 6 (depends on 5) The processor of claim 5, wherein said one or more execution units is to use the plurality of duplicated data fields from the first register to perform the second SIMD operation, either upon a fault or after each data field of the first plurality of data fields in the first register has the second value. ### Claim 7 (depends on 1) The processor of claim 1, wherein the second operation is unary. ### Claim 8 (depends on 1) The processor of claim 1, wherein the second operation is binary. ### Claim 9 (depends on 1) The processor of claim 1, wherein the data elements stored into the second register are 32-bit data elements. ### Claim 10 (depends on 1) The processor of claim 1, wherein the data elements stored into the second register are 64-bit data elements. ### Claim 11 (depends on 1) The processor of claim 1, wherein the second register is a 512-bit vector register. ### Claim 12 A machine-readable medium to record functional descriptive material including a first executable instruction, which if executed by a machine cause the machine to: read values of each data field of a first plurality of data fields in a first register, wherein each of the first plurality of data fields in the first register corresponds to a multiple of a stride length from a beginning address for a corresponding data element in a memory, and wherein for each data field in the first register, a first value indicates the corresponding element has not been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory; for each data field of the plurality of data fields in the first register having the first value, load the corresponding data element from the memory and store the corresponding data element into a second register, the second register having a second plurality of data fields, a portion of which to store the loaded data elements, and change the value of the corresponding data field in the first register from the first value to the second value; and then perform a second single-instruction-multiple-data (SIMD) operation using the data elements stored in said portion of the second plurality of data fields to generate corresponding result data elements. ### Claim 13 (depends on 12) The machine-readable medium of claim 12, the first executable instruction, if executed by the machine further causes the machine to: duplicate the plurality of data fields in the first register. ### Claim 14 (depends on 12) The machine-readable medium of claim 12, the first executable instruction, if executed by the machine further causes the machine to: duplicate each of the plurality of data fields having the first value in the first register when the value of that data field in the first register is changed from the first value to the second value. ### Claim 15 (depends on 14) The machine-readable medium of claim 14, the first executable instruction, if executed by the machine further causes the machine to: use the plurality of duplicated data fields from the first register to perform the second SIMD operation, either upon a fault or after each data field of the first plurality of data fields in the first register has the second value. ### Claim 16 (depends on 12) The machine-readable medium of claim 12, wherein the second operation is unary. ### Claim 17 (depends on 12) The machine-readable medium of claim 12, wherein the second operation is binary. ### Claim 18 (depends on 12) The machine-readable medium of claim 12, wherein the data elements stored into the second register are 32-bit data elements. ### Claim 19 (depends on 12) The machine-readable medium of claim 12, wherein the data elements stored into the second register are 64-bit data elements. ### Claim 20 (depends on 12) The machine-readable medium of claim 12, wherein the second register is a 512-bit vector register. ### Claim 21 A processor comprising: a decode stage to decode a first single-instruction-multiple-data (SIMD) instruction specifying: a set of load operations and a second SIMD operation, a destination register, an operand register, a memory address, and a stride length; and one or more execution units, responsive to the decoded first SIMD instruction, to: read values of each data field of a first plurality of data fields in a mask register, wherein each of the first plurality of data fields in the mask register wherein each of the first plurality of data fields in the first register corresponds to a multiple of the stride length from the memory address for a corresponding data element in a memory, and wherein for each data field in the mask register, a first value indicates the corresponding element has not been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory; for each data field of the plurality of data fields in the mask register having the first value, load the corresponding data element from the memory into a corresponding data field in the destination register, and change the value of the data field in the mask register from the first value to the second value; and perform the second SIMD operation using the data elements loaded into the destination register and corresponding data elements in the operand register to generate corresponding result data elements. ### Claim 22 (depends on 21) The processor of claim 21, said one or more execution units, responsive to the decoded first SIMD instruction, to duplicate the plurality of data fields in the mask register. ### Claim 23 (depends on 22) The processor of claim 22, said one or more execution units, responsive to the decoded first SIMD instruction, to duplicate each of the plurality of data fields having the first value in the mask register when the value of that data field in the mask register is changed from the first value to the second value. ### Claim 24 (depends on 23) The processor of claim 23, wherein said one or more execution units is to use the plurality of duplicated data fields from the mask register to perform the second SIMD operation, either upon a fault or after each data field of the first plurality of data fields in the mask register has the second value. ### Claim 25 (depends on 21) The processor of claim 21, wherein the data element stored into the second register are 32-bit data elements. ### Claim 26 (depends on 21) The processor of claim 21, wherein the data element stored into the second register are 64-bit data elements. ### Claim 27 (depends on 21) The processor of claim 21, wherein the second register is a 512-bit vector register. ### Claim 28 A processing system comprising: a memory; and a plurality of processors each comprising: a decode stage to decode a first single-instruction-multiple-data (SIMD) instruction specifying: a set of load operations and a second SIMD operation, a destination register, an operand register, a memory address, and a stride length; and one or more execution units, responsive to the decoded first SIMD instruction, to: read values of each data field of a first plurality of data fields in a mask register, wherein each of the first plurality of data fields in the mask register wherein each of the first plurality of data fields in the first register corresponds to a multiple of the stride length from the memory address for a corresponding data element in a memory, and wherein for each data field in the mask register, a first value indicates the corresponding element has not been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory; for each data field of the plurality of data fields in the mask register having the first value, load the corresponding data element from the memory into a corresponding data field in the destination register, and change the value of the data field in the mask register from the first value to the second value; and perform the second SIMD operation using the data elements loaded into the destination register and corresponding data elements in the operand register to generate corresponding result data elements. ### Claim 29 (depends on 28) The processing system of claim 28, said one or more execution units, further responsive to the first SIMD instruction to: duplicate each of the plurality of data fields having the first value in the mask register when the value of that data field in the mask register is changed from the first value to the second value. ### Claim 30 (depends on 29) The processing system of claim 29, said one or more execution units, further responsive to the first SIMD instruction to: use the plurality of duplicated data fields from the mask register to perform the second SIMD operation, either upon a fault or after each data field of the first plurality of data fields in the mask register has the second value.