# US 2014/0195777 A1 · Variable depth instruction fifos to implement simd architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0195777 A1 - Document ID: US20140195777A1 - Status: Published application - Kind: A1 - Application number: 13/738,239 - Filed: 2013-01-10 - Published: 2014-07-10 - Earliest claimed: 2013-01-10 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Mark D. Bellows; Mark S. Fredrickson; Scott D. Frei; Steven P. Jones; Chad B. McBride - Web page: https://patentgrep.com/patent/US20140195777A1 ## CPC - G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors} - G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead - G06F 9/3814: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3853: {of compound instructions} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3889: {controlled by multiple instructions, e.g. MIMD, decoupled access or execute} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In a particular embodiment, a method may include creating a plurality of variable depth instruction FIFOs and a plurality of data caches from a plurality of caches corresponding to a plurality of processors, where the plurality of caches and the plurality of processors correspond to MIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs to implement SIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs for at least one of SIMD operation, SIMD operation with staging, or RC-SIMD operation. ## Claims ### Claim 1 A method, comprising: creating a plurality of variable depth instruction FIFOs and a plurality of data caches from a plurality of caches corresponding to a plurality of processors, wherein the plurality of caches and the plurality of processors correspond to MIMD architecture; and configuring the plurality of variable depth instruction FIFOs to implement SIMD architecture. ### Claim 2 (depends on 1) The method of claim 1, further comprising configuring the plurality of variable depth instruction FIFOs for at least one of SIMD operation, SIMD operation with staging, or RC-SIMD operation. ### Claim 3 (depends on 1) The method of claim 1, further comprising determining a depth for at least one variable depth instruction FIFO. ### Claim 4 (depends on 3) The method of claim 3, further comprising configuring at least one variable depth instruction FIFO with the determined depth. ### Claim 5 (depends on 3) The method of claim 3, further comprising configuring at least one variable depth instruction FIFO with a depth that is different than the determined depth. ### Claim 6 (depends on 3) The method of claim 3, further comprising determining the depth for at least one variable depth instruction FIFO by dynamically growing a variable depth instruction FIFO. ### Claim 7 (depends on 3) The method of claim 3, further comprising determining the depth for at least one variable depth instruction FIFO by dynamically shrinking a variable depth instruction FIFO. ### Claim 8 (depends on 1) The method of claim 1, further comprising determining a tap depth for at least one variable depth instruction FIFO. ### Claim 9 (depends on 1) The method of claim 1, further comprising determining a number of processor cores to utilize for a particular workload for a RC-SIMD operation. ### Claim 10 (depends on 1) The method of claim 1, further comprising configuring the plurality of variable depth instruction FIFOs to cascade an instruction, including configuring a first variable depth instruction FIFO to cascade the instruction within the first variable depth instruction FIFO and to cascade the instruction to a second variable depth instruction FIFO. ### Claim 11 (depends on 1) The method of claim 1, further comprising configuring the plurality of variable depth instruction FIFOs to adjust timing of an instruction to enable each processor core of the plurality of processor cores to receive the instruction at an appropriate time. ### Claim 12 An apparatus, comprising: a memory storing program code; and a processor configured to access the memory and execute the program code to create a plurality of variable depth instruction FIFOs and a plurality of data caches from a plurality of caches corresponding to a plurality of processors, wherein the plurality of caches and the plurality of processors correspond to MIMD architecture, and to configure the plurality of variable depth instruction FIFOs to implement SIMD architecture. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the processor is configured to execute the program code to configure the plurality of variable depth instruction FIFOs for at least one of SIMD operation, SIMD operation with staging, or RC-SIMD operation. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the processor is configured to execute the program code to determine a depth for at least one variable depth instruction FIFO. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the processor is configured to execute the program code to determine the depth for at least one variable depth instruction FIFO by dynamically growing a variable depth instruction FIFO. ### Claim 16 (depends on 12) The apparatus of claim 12, wherein the processor is configured to execute the program code to determine a tap depth for at least one variable depth instruction FIFO. ### Claim 17 (depends on 12) The apparatus of claim 12, wherein the processor is configured to execute the program code to determine a number of processor cores to utilize for a particular workload for RC-SIMD operation. ### Claim 18 (depends on 12) The apparatus of claim 12, wherein the processor is configured to execute the program code to configure the plurality of variable depth instruction FIFOs to cascade an instruction, including configuring a first variable depth instruction FIFO to cascade the instruction within the first variable depth instruction FIFO and to cascade the instruction to a second variable depth instruction FIFO. ### Claim 19 (depends on 12) The apparatus of claim 12, wherein the processor is configured execute the program code to configure the plurality of variable depth instruction FIFOs to adjust timing of an instruction to enable each processor core of the plurality of processor cores to receive the instruction at an appropriate time. ### Claim 20 An apparatus, comprising: a plurality of variable depth instruction FIFOs and a plurality of data caches created from a plurality of caches corresponding to a plurality of processors, including a first variable depth instruction FIFO, a second variable depth instruction FIFO, and a third variable depth instruction FIFO, and wherein the plurality of caches and the plurality of processors correspond to MIMD architecture; the first variable depth instruction FIFO configured to cascade an instruction within the first variable depth instruction FIFO and to cascade the instruction to the second variable depth instruction FIFO to implement SIMD architecture; and the second variable depth instruction FIFO configured to cascade the instruction within the second variable depth instruction FIFO and to cascade the instruction to a third variable depth instruction FIFO to implement SIMD architecture.