# US 2014/0195776 A1 · Memory access for a vector processor

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- Number: US 2014/0195776 A1
- Document ID: US20140195776A1
- Status: Published application
- Kind: A1
- Application number: 13/737,290
- Filed: 2013-01-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: Cognivue Corporation
- Applicants: Cognivue Corporation
- Inventors: Malcolm STEWART; Ali Osman ORS; Daniel LAROCHE
- Web page: https://patentgrep.com/patent/US20140195776A1

## CPC

- G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters}
- G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file}
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/3824: {Operand accessing}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 15/8061: {Details on data memory access}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.

## Claims

### Claim 1

A device comprising:
a vector memory space divided into a plurality of memory macro-blocks for storing data;
a vector processor comprising a plurality of computational units (CUs) for executing instructions, the plurality of CUs arranged into a plurality of CU groups, each CU group comprising two or more CUs of the plurality of CUs, the plurality of CUs providing execution of a single instruction on multiple pieces of data (SIMD); and
a plurality of memory macro-block access units, each coupling a respective CU group to a respective associated memory macro-block, for controlling access of the CUs of the respective CU group to the associated memory macro-block.

### Claim 2 (depends on 1)

The device of claim 1, wherein each of the memory macro-block access units determines an address within the associated memory macro-block to retrieve data from or place data to.

### Claim 3 (depends on 2)

The device of claim 2, wherein each of the memory macro-block access units determines the address individually for each CU in the associated CU group in subsequent cycles.

### Claim 4 (depends on 2)

The device of claim 2, wherein each of the memory macro-block access units determines the address for two or more CUs in the associated CU group in a single cycle.

### Claim 5 (depends on 1)

The device of claim 1, wherein there are z CU groups, each with m CUs, each of the CUs has an n-bit interface to the associated memory macro-block, wherein each of the memory macro-blocks can provide n×m bits of data to the associated CU group in a memory access operation, wherein the n×m bits of data for a respective CU group are addressed by a single memory macro-block address.

### Claim 6 (depends on 5)

The device of claim 5, wherein each of the memory macro-block access units controls data provided to, or received from, each of the CUs in the respective CU group based on a CU mask indicating a portion of the m×n bits of data from the associated memory macro-block the respective CU is to receive.

### Claim 7 (depends on 1)

The device of claim 1, wherein each of the memory macro-block access units can access data from neighboring memory macro-blocks during a portion of a memory access operation.

### Claim 8 (depends on 7)

The device of claim 7, wherein each of the memory macro-block access units determines the address from the respective neighboring memory macro-block for two or more CUs in the associated CU group in a single cycle.

### Claim 9 (depends on 1)

The device of claim 1, wherein each of the memory macro-block access units can access data from a plurality of neighboring memory macro-blocks during a portion of a memory access operation.

### Claim 10 (depends on 9)

The device of claim 9, wherein each memory macro-block access unit has a plurality of neighbors.

### Claim 11

A method comprising:
initiating a read operation for loading data from memory into a plurality of computational units (CUs) arranged into a plurality of CU groups, the memory arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups;
for each CU group, determining a respective first memory address; and
for each CU group, accessing the data in the associated memory macro-block at the respective first memory address.

### Claim 12 (depends on 11)

The method of claim 11, wherein accessing the data comprises reading data from the respective memory macro-block or providing data to the respective memory macro-block.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
reading data from the respective memory macro-block to a first CU of the respective CU group or providing data to the respective memory macro-block from the first CU of the respective CU group, wherein the first memory address is associated with the first CU;
for each CU group, determining a respective second memory address associated with a respective second CU in the CU group; and
reading data from the respective memory macro-block to the second CU of the respective CU group or providing data to the respective memory macro-block from the second CU of the respective CU group.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first and second addresses are individually determined for each of the first and second CUs in the associated CU group in subsequent cycles.

### Claim 15 (depends on 11)

The method of claim 11, wherein the first address is determined for two or more CUs in the associated CU group in a single cycle.

### Claim 16 (depends on 11)

The method of claim 11, wherein there are z CU groups, each with m CUs, each of the CUs has an n-bit interface to the associated memory macro-block, wherein each of the memory macro-blocks can provide n×m bits of data to the associated CU group in a memory access operation, wherein the n×m bits of data for a respective CU group are addressed by a single memory macro-block address.

### Claim 17 (depends on 11)

The method of claim 11, further comprising controlling data provided to, or received from, each of the CUs in the respective CU group based on a CU mask indicating a portion of the m×n bits of data from the associated memory macro-block the respective CU is to receive.

### Claim 18 (depends on 11)

The method of claim 11, further comprising accessing data from a respective neighboring memory macro-block during a portion of a memory access operation.

### Claim 19 (depends on 18)

The method of claim 18, determining an address from the respective neighboring memory macro-block for two or more CUs in the associated CU group in a single cycle.

### Claim 20 (depends on 11)

The method of claim 11, further comprising accessing data from one of a plurality of neighboring memory macro-blocks during a portion of a memory access operation.