# US 2014/0195775 A1 · Instruction and logic to provide vector loads and stores with strides and masking functionality

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0195775 A1
- Document ID: US20140195775A1
- Status: Published application
- Kind: A1
- Application number: 13/977,730
- Filed: 2011-09-26
- Published: 2014-07-10
- Earliest claimed: 2011-09-26
- Assignees: Intel Corporation
- Inventors: Elmoustapha Ould-Ahmed-Vall; Kshitij A. Doshi; Suleyman Sair; Charles R. Yount
- Web page: https://patentgrep.com/patent/US20140195775A1

## CPC

- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30018: {Bit or string instructions}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30101: {Special purpose registers}
- G06F 9/3455: {using stride}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the corresponding multiple of said stride length is generated according to the data field's position in the mask register to load the data element from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. These instructions can restart after faults.

## Claims

### Claim 1

A processor comprising:
a completion mask register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the completion mask register corresponds to a multiple of a stride length from a beginning address for a corresponding data element in a memory, wherein for each data field in the completion mask register, a first value indicates the corresponding element has not yet been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory;
a decode stage to decode a first instruction specifying the completion mask register, the stride length and a set of load operations corresponding to one or more of the first plurality of data fields; and
one or more execution units, responsive to the decoded first instruction, to:
read the values of each of the data fields in the completion mask register;
for each data field of the first plurality of data fields in the completion mask register having the first value, compute the corresponding multiple of said stride length according to a position of the data field in the completion mask register to load the corresponding data element from the memory and store the corresponding data element into a destination register, the destination register having a second plurality of data fields, a portion of which to store the loaded data elements, and to
change the value of the corresponding data field in the completion mask register from the first value to the second value.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the first value is one.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the second value is zero.

### Claim 4 (depends on 1)

The processor of claim 1, said one or more execution units, responsive to the decoded first instruction, to store each loaded data element into one of the second plurality of data fields in the destination register at a position corresponding to the position of the corresponding data field in the completion mask register.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the data elements stored into the destination register are 32-bit data elements.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the data elements stored into the destination register are 64-bit data elements.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the data elements stored into the destination register are 8-bit data elements.

### Claim 8 (depends on 1)

The processor of claim 1, wherein the data elements stored into the destination register are 16-bit data elements.

### Claim 9 (depends on 1)

The processor of claim 1, wherein the destination register is a 128-bit vector register.

### Claim 10 (depends on 1)

The processor of claim 1, wherein the destination register is a 256-bit vector register.

### Claim 11 (depends on 1)

The processor of claim 1, wherein the destination register is a 512-bit vector register.

### Claim 12

A machine-readable medium to record functional descriptive material including a first executable instruction, which if executed by a machine causes the machine to:
read values of each data field of a first plurality of data fields in a first register, wherein each of the first plurality of data fields in the first register corresponds to a multiple of a stride length from a beginning address for a corresponding data element in a memory, and wherein for each data field in the first register, a first value indicates the corresponding element has not been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory; and
for each data field of the plurality of data fields in the first register having the first value, compute the corresponding multiple of said stride length according to a position of the data field in the first register to load the corresponding data element from the memory and store the corresponding data element into a second register, the second register having a second plurality of data fields, a portion of which to store the loaded data elements, and
change the value of the corresponding data field in the first register from the first value to the second value.

### Claim 13 (depends on 12)

The machine-readable medium of claim 12, the first executable instruction, if executed by the machine further causes the machine to:
store each loaded data element into one of the second plurality of data fields in the second register at a position corresponding to the position of the corresponding data field in the first register.

### Claim 14 (depends on 13)

The machine-readable medium of claim 13, wherein the data elements stored into the second register are 32-bit data elements.

### Claim 15 (depends on 13)

The machine-readable medium of claim 13, wherein the data elements stored into the second register are 64-bit data elements.

### Claim 16 (depends on 13)

The machine-readable medium of claim 13, wherein the second register is a 128-bit vector register.

### Claim 17 (depends on 13)

The machine-readable medium of claim 13, wherein the second register is a 256-bit vector register.

### Claim 18 (depends on 13)

The machine-readable medium of claim 13, wherein the second register is a 512-bit vector register.

### Claim 19

A processor comprising:
a decode stage to decode a first single-instruction-multiple-data (SIMD) instruction specifying: a set of load operations, a destination register, a memory address, and a stride length; and
one or more execution units, responsive to the decoded first SIMD instruction, to:
read values of each data field of a first plurality of data fields in a mask register, wherein each of the first plurality of data fields in the mask register wherein each of the first plurality of data fields in the first register corresponds to a multiple of the stride length from the memory address for a corresponding data element in a memory, and wherein for each data field in the mask register, a first value indicates the corresponding element has not been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory;
for each data field of the plurality of data fields in the mask register having the first value, compute the corresponding multiple of said stride length according to a position of the data field in the mask register to load the corresponding data element from the memory into a corresponding data field in the destination register, and change the value of the data field in the mask register from the first value to the second value.

### Claim 20 (depends on 19)

The processor of claim 19, said one or more execution units, responsive to the decoded first SIMD instruction, to store each loaded data element into one of the second plurality of data fields in the second register at a position corresponding to the position of the corresponding data field in the mask register.

### Claim 21 (depends on 20)

The processor of claim 20, wherein the data element stored into the second register are 64-bit data elements.

### Claim 22 (depends on 20)

The processor of claim 20, wherein the second register is a 128-bit vector register.

### Claim 23 (depends on 20)

The processor of claim 20, wherein the second register is a 256-bit vector register.

### Claim 24 (depends on 20)

The processor of claim 20, wherein the second register is a 512-bit vector register.

### Claim 25

A processing system comprising:
a memory; and
a plurality of processors each comprising:
a decode stage to decode a first SIMD instruction specifying: a set of load operations, a destination register, a mask register, a memory address, and a stride length; and
one or more execution units, responsive to the decoded first SIMD instruction, to:
read values of each data field of a first plurality of data fields in the mask register, wherein each of the first plurality of data fields in the mask register wherein each of the first plurality of data fields in the first register corresponds to a multiple of the stride length from the memory address for a corresponding data element in a memory, and wherein for each data field in the mask register, a first value indicates the corresponding element has not been loaded from the memory and a second value indicates that the corresponding data element does not need to be loaded, or has already been loaded from the memory;
for each data field of the plurality of data fields in the mask register having the first value, compute the corresponding multiple of said stride length according to a position of the data field in the mask register to load the corresponding data element from the memory into a corresponding data field in the destination register, and change the value of the data field in the mask register from the first value to the second value.

### Claim 26 (depends on 25)

The processing system of claim 25, said one or more execution units, further responsive to the first SIMD instruction to:
store each loaded data element into one of a second plurality of data fields in the destination register at a position corresponding to the position of the corresponding data field in the mask register.

### Claim 27 (depends on 25)

The processing system of claim 25, wherein the data element stored into the destination register are 32-bit data elements.

### Claim 28 (depends on 25)

The processing system of claim 25, wherein the destination register is a 128-bit vector register.

### Claim 29 (depends on 25)

The processing system of claim 25, wherein the destination register is a 256-bit vector register.

### Claim 30 (depends on 25)

The processing system of claim 25, wherein the destination register is a 512-bit vector register.